mirror of https://github.com/ipxe/ipxe.git
Set up %ds *before* testing a value in our data segment (d'oh!).
Always send EOI; do not chain to BIOS's default interrupt handler. They are just too unpredictable; at least VMware's seems to kill the machine if you go anywhere near it. Disable interrupts after return from PXENV_UNDI_ISR, just in case some dumb PXE stack enables them.pull/1/head
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f6f9a3098d
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@ -23,14 +23,17 @@ undiisr:
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pushw %es
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pushw %es
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pusha
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pusha
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/* Set up our segment registers */
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movw %cs:rm_ds, %ax
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movw %ax, %ds
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/* Check that we have an UNDI entry point */
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/* Check that we have an UNDI entry point */
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cmpw $0, undinet_entry_point
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cmpw $0, undinet_entry_point
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je chain
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je chain
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/* Issue UNDI API call */
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/* Issue UNDI API call */
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movw %cs:rm_ds, %ax
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pushw %ds
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movw %ax, %ds
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popw %es
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movw %ax, %es
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movw $undinet_params, %di
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movw $undinet_params, %di
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movw $PXENV_UNDI_ISR, %bx
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movw $PXENV_UNDI_ISR, %bx
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movw $PXENV_UNDI_ISR_IN_START, funcflag
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movw $PXENV_UNDI_ISR_IN_START, funcflag
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@ -38,13 +41,15 @@ undiisr:
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pushw %di
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pushw %di
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pushw %bx
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pushw %bx
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lcall *undinet_entry_point
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lcall *undinet_entry_point
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cli /* Just in case */
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addw $6, %sp
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addw $6, %sp
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cmpw $PXENV_UNDI_ISR_OUT_OURS, funcflag
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cmpw $PXENV_UNDI_ISR_OUT_OURS, funcflag
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jne chain
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jne eoi
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ack: /* Record interrupt occurence */
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trig: /* Record interrupt occurence */
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incb undiisr_trigger_count
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incb undiisr_trigger_count
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/* Send EOI */
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eoi: /* Send EOI */
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movb $ICR_EOI_NON_SPECIFIC, %al
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movb $ICR_EOI_NON_SPECIFIC, %al
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cmpb $IRQ_PIC_CUTOFF, undiisr_irq
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cmpb $IRQ_PIC_CUTOFF, undiisr_irq
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jb 1f
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jb 1f
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