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[ena] Increase receive ring size to 128 entries 

Some versions of the ENA hardware (observed on a c6i.large instance in
eu-west-2) seem to require a receive ring containing at least 128
entries: any smaller ring will never see receive completions or will
stall after the first few completions.

Increase the receive ring size to 128 entries (determined empirically)
for compatibility with these hardware versions.  Limit the receive
ring fill level to 16 (as at present) to avoid consuming more memory
than will typically be available in the internal heap.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
pull/732/head
Michael Brown 2022-08-26 13:17:48 +01:00
parent 3b81a4e256
commit a80124456e
2 changed files with 12 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/drivers/net/ena.c
View File

@ -395,7 +395,7 @@ static int ena_create_sq ( struct ena_nic *ena, struct ena_sq *sq,
sq->phase = ENA_SQE_PHASE; sq->phase = ENA_SQE_PHASE;
/* Calculate fill level */ /* Calculate fill level */
sq->fill = sq->count; sq->fill = sq->max;
if ( sq->fill > cq->actual ) if ( sq->fill > cq->actual )
sq->fill = cq->actual; sq->fill = cq->actual;
@ -1010,11 +1010,11 @@ static int ena_probe ( struct pci_device *pci ) {
ena->acq.phase = ENA_ACQ_PHASE; ena->acq.phase = ENA_ACQ_PHASE;
ena_cq_init ( &ena->tx.cq, ENA_TX_COUNT, ena_cq_init ( &ena->tx.cq, ENA_TX_COUNT,
sizeof ( ena->tx.cq.cqe.tx[0] ) ); sizeof ( ena->tx.cq.cqe.tx[0] ) );
ena_sq_init ( &ena->tx.sq, ENA_SQ_TX, ENA_TX_COUNT, ena_sq_init ( &ena->tx.sq, ENA_SQ_TX, ENA_TX_COUNT, ENA_TX_COUNT,
sizeof ( ena->tx.sq.sqe.tx[0] ), ena->tx_ids ); sizeof ( ena->tx.sq.sqe.tx[0] ), ena->tx_ids );
ena_cq_init ( &ena->rx.cq, ENA_RX_COUNT, ena_cq_init ( &ena->rx.cq, ENA_RX_COUNT,
sizeof ( ena->rx.cq.cqe.rx[0] ) ); sizeof ( ena->rx.cq.cqe.rx[0] ) );
ena_sq_init ( &ena->rx.sq, ENA_SQ_RX, ENA_RX_COUNT, ena_sq_init ( &ena->rx.sq, ENA_SQ_RX, ENA_RX_COUNT, ENA_RX_FILL,
sizeof ( ena->rx.sq.sqe.rx[0] ), ena->rx_ids ); sizeof ( ena->rx.sq.sqe.rx[0] ), ena->rx_ids );
/* Fix up PCI device */ /* Fix up PCI device */

11
src/drivers/net/ena.h
View File

@ -28,7 +28,10 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#define ENA_TX_COUNT 16 #define ENA_TX_COUNT 16
/** Number of receive queue entries */ /** Number of receive queue entries */
#define ENA_RX_COUNT 16 #define ENA_RX_COUNT 128
/** Receive queue maximum fill level */
#define ENA_RX_FILL 16
/** Base address low register offset */ /** Base address low register offset */
#define ENA_BASE_LO 0x0 #define ENA_BASE_LO 0x0
@ -608,6 +611,8 @@ struct ena_sq {
uint8_t direction; uint8_t direction;
/** Number of entries */ /** Number of entries */
uint8_t count; uint8_t count;
/** Maximum fill level */
uint8_t max;
/** Fill level (limited to completion queue size) */ /** Fill level (limited to completion queue size) */
uint8_t fill; uint8_t fill;
}; };
@ -618,16 +623,18 @@ struct ena_sq {
* @v sq Submission queue * @v sq Submission queue
* @v direction Direction * @v direction Direction
* @v count Number of entries * @v count Number of entries
* @v max Maximum fill level
* @v size Size of each entry * @v size Size of each entry
* @v ids Buffer IDs * @v ids Buffer IDs
*/ */
static inline __attribute__ (( always_inline )) void static inline __attribute__ (( always_inline )) void
ena_sq_init ( struct ena_sq *sq, unsigned int direction, unsigned int count, ena_sq_init ( struct ena_sq *sq, unsigned int direction, unsigned int count,
size_t size, uint8_t *ids ) { unsigned int max, size_t size, uint8_t *ids ) {
sq->len = ( count * size ); sq->len = ( count * size );
sq->direction = direction; sq->direction = direction;
sq->count = count; sq->count = count;
sq->max = max;
sq->ids = ids; sq->ids = ids;
} }