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[intelxl] Always issue "clear PXE mode" admin queue command 

Remove knowledge of the GLLAN_RCTL_0 register (which changes location
between the XL810 and E810 register maps), and instead unconditionally
issue the "clear PXE mode" command with the EEXIST error silenced.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
pull/697/head^2
Michael Brown 2022-03-17 13:11:21 +00:00
parent faf26bf8b8
commit 99242bbe2e
2 changed files with 11 additions and 13 deletions
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17
src/drivers/net/intelxl.c
View File

@ -544,20 +544,12 @@ static int intelxl_admin_shutdown ( struct intelxl_nic *intelxl ) {
static int intelxl_admin_clear_pxe ( struct intelxl_nic *intelxl ) {
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_clear_pxe_params *pxe;
uint32_t gllan_rctl_0;
int rc;
/* Do nothing if device is already out of PXE mode */
gllan_rctl_0 = readl ( intelxl->regs + INTELXL_GLLAN_RCTL_0 );
if ( ! ( gllan_rctl_0 & INTELXL_GLLAN_RCTL_0_PXE_MODE ) ) {
DBGC2 ( intelxl, "INTELXL %p already in non-PXE mode\n",
intelxl );
return 0;
}
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_CLEAR_PXE );
cmd->ret = cpu_to_le16 ( INTELXL_ADMIN_EEXIST );
pxe = &cmd->params.pxe;
pxe->magic = INTELXL_ADMIN_CLEAR_PXE_MAGIC;
@ -565,6 +557,13 @@ static int intelxl_admin_clear_pxe ( struct intelxl_nic *intelxl ) {
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
/* Check for expected errors */
if ( cmd->ret == cpu_to_le16 ( INTELXL_ADMIN_EEXIST ) ) {
DBGC ( intelxl, "INTELXL %p already in non-PXE mode\n",
intelxl );
return 0;
}
return 0;
}

7
src/drivers/net/intelxl.h
View File

@ -377,6 +377,9 @@ struct intelxl_admin_descriptor {
/** Admin descriptor uses data buffer */
#define INTELXL_ADMIN_FL_BUF 0x1000
/** Error: attempt to create something that already exists */
#define INTELXL_ADMIN_EEXIST 13
/** Admin queue */
struct intelxl_admin {
/** Descriptors */
@ -577,10 +580,6 @@ struct intelxl_context_rx {
/** Queue Tail Pointer Register (offset) */
#define INTELXL_QXX_TAIL 0x8000
/** Global RLAN Control 0 register */
#define INTELXL_GLLAN_RCTL_0 0x12a500
#define INTELXL_GLLAN_RCTL_0_PXE_MODE 0x00000001UL /**< PXE mode */
/** Transmit data descriptor */
struct intelxl_tx_data_descriptor {
/** Buffer address */