mirror of https://github.com/ipxe/ipxe.git
[intelxl] Choose to operate in non-PXE mode
The physical function defaults to operating in "PXE mode" after a power-on reset. In this mode, receive descriptors are fetched and written back as single descriptors. In normal (non-PXE mode) operation, receive descriptors are fetched and written back only as complete cachelines unless an interrupt is raised. There is no way to return to PXE mode from non-PXE mode, and there is no way for the virtual function driver to operate in PXE mode. Choose to operate in non-PXE mode. This requires us to trick the hardware into believing that it is raising an interrupt, so that it will not defer writing back receive descriptors until a complete cacheline (i.e. four packets) have been consumed. We do so by configuring the hardware to use MSI-X with a dummy target location in place of the usual APIC register. Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/92/head
Michael Brown
parent
3078a952a8
commit
92b46b7858
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@ -116,6 +116,56 @@ static int intelxl_fetch_mac ( struct intelxl_nic *intelxl,
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return 0;
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}
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/******************************************************************************
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*
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* MSI-X interrupts
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*
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******************************************************************************
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*/
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/**
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* Enable MSI-X dummy interrupt
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*
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* @v intelxl Intel device
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* @v pci PCI device
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* @ret rc Return status code
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*/
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int intelxl_msix_enable ( struct intelxl_nic *intelxl,
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struct pci_device *pci ) {
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int rc;
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/* Enable MSI-X capability */
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if ( ( rc = pci_msix_enable ( pci, &intelxl->msix ) ) != 0 ) {
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DBGC ( intelxl, "INTELXL %p could not enable MSI-X: %s\n",
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intelxl, strerror ( rc ) );
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return rc;
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}
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/* Configure interrupt zero to write to dummy location */
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pci_msix_map ( &intelxl->msix, 0, virt_to_bus ( &intelxl->msg ), 0 );
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/* Enable dummy interrupt zero */
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pci_msix_unmask ( &intelxl->msix, 0 );
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return 0;
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}
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/**
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* Disable MSI-X dummy interrupt
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*
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* @v intelxl Intel device
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* @v pci PCI device
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*/
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void intelxl_msix_disable ( struct intelxl_nic *intelxl,
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struct pci_device *pci ) {
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/* Disable dummy interrupt zero */
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pci_msix_mask ( &intelxl->msix, 0 );
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/* Disable MSI-X capability */
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pci_msix_disable ( pci, &intelxl->msix );
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}
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/******************************************************************************
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*
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* Admin queue
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@ -480,6 +530,39 @@ static int intelxl_admin_shutdown ( struct intelxl_nic *intelxl ) {
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return 0;
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}
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/**
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* Clear PXE mode
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*
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* @v intelxl Intel device
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* @ret rc Return status code
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*/
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static int intelxl_admin_clear_pxe ( struct intelxl_nic *intelxl ) {
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struct intelxl_admin_descriptor *cmd;
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struct intelxl_admin_clear_pxe_params *pxe;
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uint32_t gllan_rctl_0;
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int rc;
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/* Do nothing if device is already out of PXE mode */
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gllan_rctl_0 = readl ( intelxl->regs + INTELXL_GLLAN_RCTL_0 );
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if ( ! ( gllan_rctl_0 & INTELXL_GLLAN_RCTL_0_PXE_MODE ) ) {
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DBGC2 ( intelxl, "INTELXL %p already in non-PXE mode\n",
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intelxl );
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return 0;
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}
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/* Populate descriptor */
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cmd = intelxl_admin_command_descriptor ( intelxl );
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cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_CLEAR_PXE );
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pxe = &cmd->params.pxe;
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pxe->magic = INTELXL_ADMIN_CLEAR_PXE_MAGIC;
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/* Issue command */
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if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
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return rc;
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return 0;
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}
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/**
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* Get switch configuration
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*
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@ -1504,13 +1587,6 @@ static void intelxl_poll_rx ( struct net_device *netdev ) {
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void intelxl_poll ( struct net_device *netdev ) {
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struct intelxl_nic *intelxl = netdev->priv;
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/* Acknowledge interrupts, if applicable */
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if ( netdev_irq_enabled ( netdev ) ) {
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writel ( ( INTELXL_INT_DYN_CTL_CLEARPBA |
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INTELXL_INT_DYN_CTL_INTENA_MASK ),
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( intelxl->regs + intelxl->intr ) );
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}
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/* Poll for completed packets */
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intelxl_poll_tx ( netdev );
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@ -1522,19 +1598,23 @@ void intelxl_poll ( struct net_device *netdev ) {
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/* Refill RX ring */
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intelxl_refill_rx ( intelxl );
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}
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/**
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* Enable or disable interrupts
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/* Rearm interrupt, since otherwise receive descriptors will
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* be written back only after a complete cacheline (four
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* packets) have been received.
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*
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* @v netdev Network device
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* @v enable Interrupts should be enabled
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* There is unfortunately no efficient way to determine
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* whether or not rearming the interrupt is necessary. If we
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* are running inside a hypervisor (e.g. using a VF or PF as a
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* passed-through PCI device), then the MSI-X write is
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* redirected by the hypervisor to the real host APIC and the
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* host ISR then raises an interrupt within the guest. We
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* therefore cannot poll the nominal MSI-X target location to
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* watch for the value being written. We could read from the
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* INT_DYN_CTL register, but this is even less efficient than
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* just unconditionally rearming the interrupt.
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*/
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static void intelxl_irq ( struct net_device *netdev, int enable ) {
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struct intelxl_nic *intelxl = netdev->priv;
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writel ( ( enable ? INTELXL_INT_DYN_CTL_INTENA : 0 ),
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( intelxl->regs + intelxl->intr ) );
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writel ( INTELXL_INT_DYN_CTL_INTENA, intelxl->regs + intelxl->intr );
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}
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/** Network device operations */
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@ -1543,7 +1623,6 @@ static struct net_device_operations intelxl_operations = {
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.close = intelxl_close,
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.transmit = intelxl_transmit,
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.poll = intelxl_poll,
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.irq = intelxl_irq,
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};
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/******************************************************************************
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@ -1617,10 +1696,18 @@ static int intelxl_probe ( struct pci_device *pci ) {
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if ( ( rc = intelxl_fetch_mac ( intelxl, netdev ) ) != 0 )
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goto err_fetch_mac;
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/* Enable MSI-X dummy interrupt */
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if ( ( rc = intelxl_msix_enable ( intelxl, pci ) ) != 0 )
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goto err_msix;
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/* Open admin queues */
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if ( ( rc = intelxl_open_admin ( intelxl ) ) != 0 )
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goto err_open_admin;
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/* Clear PXE mode */
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if ( ( rc = intelxl_admin_clear_pxe ( intelxl ) ) != 0 )
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goto err_admin_clear_pxe;
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/* Get switch configuration */
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if ( ( rc = intelxl_admin_switch ( intelxl ) ) != 0 )
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goto err_admin_switch;
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@ -1667,8 +1754,11 @@ static int intelxl_probe ( struct pci_device *pci ) {
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err_admin_promisc:
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err_admin_vsi:
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err_admin_switch:
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err_admin_clear_pxe:
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intelxl_close_admin ( intelxl );
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err_open_admin:
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intelxl_msix_disable ( intelxl, pci );
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err_msix:
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err_fetch_mac:
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intelxl_reset ( intelxl );
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err_reset:
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@ -1695,6 +1785,9 @@ static void intelxl_remove ( struct pci_device *pci ) {
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/* Close admin queues */
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intelxl_close_admin ( intelxl );
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/* Disable MSI-X dummy interrupt */
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intelxl_msix_disable ( intelxl, pci );
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/* Reset the NIC */
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intelxl_reset ( intelxl );
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@ -11,6 +11,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/if_ether.h>
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#include <ipxe/pcimsix.h>
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struct intelxl_nic;
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@ -143,6 +144,20 @@ struct intelxl_admin_shutdown_params {
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/** Driver is unloading */
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#define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
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/** Admin queue Clear PXE Mode command */
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#define INTELXL_ADMIN_CLEAR_PXE 0x0110
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/** Admin queue Clear PXE Mode command parameters */
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struct intelxl_admin_clear_pxe_params {
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/** Magic value */
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uint8_t magic;
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/** Reserved */
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uint8_t reserved[15];
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} __attribute__ (( packed ));
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/** Clear PXE Mode magic value */
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#define INTELXL_ADMIN_CLEAR_PXE_MAGIC 0x02
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/** Admin queue Get Switch Configuration command */
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#define INTELXL_ADMIN_SWITCH 0x0200
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@ -305,6 +320,8 @@ union intelxl_admin_params {
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struct intelxl_admin_driver_params driver;
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/** Shutdown command parameters */
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struct intelxl_admin_shutdown_params shutdown;
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/** Clear PXE Mode command parameters */
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struct intelxl_admin_clear_pxe_params pxe;
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/** Get Switch Configuration command parameters */
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struct intelxl_admin_switch_params sw;
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/** Get VSI Parameters command parameters */
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@ -563,6 +580,10 @@ struct intelxl_context_rx {
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/** Queue Tail Pointer Register (offset) */
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#define INTELXL_QXX_TAIL 0x8000
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/** Global RLAN Control 0 register */
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#define INTELXL_GLLAN_RCTL_0 0x12a500
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#define INTELXL_GLLAN_RCTL_0_PXE_MODE 0x00000001UL /**< PXE mode */
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/** Transmit data descriptor */
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struct intelxl_tx_data_descriptor {
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/** Buffer address */
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@ -709,22 +730,27 @@ intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count, size_t len,
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ring->context = context;
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}
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/** Number of transmit descriptors */
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#define INTELXL_TX_NUM_DESC 16
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/** Number of transmit descriptors
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*
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* Chosen to exceed the receive ring fill level, in order to avoid
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* running out of transmit descriptors when sending TCP ACKs.
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*/
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#define INTELXL_TX_NUM_DESC 64
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/** Transmit descriptor ring maximum fill level */
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#define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
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/** Number of receive descriptors
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*
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* In PXE mode (i.e. able to post single receive descriptors), 8
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* descriptors is the only permitted value covering all possible
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* numbers of PFs.
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* Must be a multiple of 32.
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*/
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#define INTELXL_RX_NUM_DESC 8
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#define INTELXL_RX_NUM_DESC 32
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/** Receive descriptor ring fill level */
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#define INTELXL_RX_FILL ( INTELXL_RX_NUM_DESC - 1 )
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/** Receive descriptor ring fill level
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*
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* Must be a multiple of 8 and greater than 8.
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*/
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#define INTELXL_RX_FILL 16
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/******************************************************************************
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*
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@ -837,6 +863,10 @@ struct intelxl_nic {
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unsigned int qset;
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/** Interrupt control register */
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unsigned int intr;
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/** MSI-X capability */
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struct pci_msix msix;
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/** MSI-X dummy interrupt target */
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uint32_t msg;
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/** Admin command queue */
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struct intelxl_admin command;
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@ -851,6 +881,10 @@ struct intelxl_nic {
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struct io_buffer *rx_iobuf[INTELXL_RX_NUM_DESC];
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};
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extern int intelxl_msix_enable ( struct intelxl_nic *intelxl,
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struct pci_device *pci );
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extern void intelxl_msix_disable ( struct intelxl_nic *intelxl,
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struct pci_device *pci );
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extern struct intelxl_admin_descriptor *
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intelxl_admin_command_descriptor ( struct intelxl_nic *intelxl );
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extern union intelxl_admin_buffer *
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