mirror of https://github.com/ipxe/ipxe.git
[etherfabric] Merge changes from vendor tree
Also clean up minor errors in the use of debug macros.pull/1/head
Michael Brown
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744b98d273
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58dd6e04c5
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/**************************************************************************
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*
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* Etherboot driver for Level 5 Etherfabric network cards
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*
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* Written by Michael Brown <mbrown@fensystems.co.uk>
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*
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* Copyright Fen Systems Ltd. 2005
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* Copyright Level 5 Networks Inc. 2005
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*
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* This software may be used and distributed according to the terms of
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* the GNU General Public License (GPL), incorporated herein by
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* reference. Drivers based on or derived from this code fall under
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* the GPL and must retain the authorship, copyright and license
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* notice.
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*
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**************************************************************************
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*/
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#ifndef EFAB_NIC_H
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#define EFAB_NIC_H
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#include <gpxe/bitbash.h>
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#include <gpxe/i2c.h>
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#include <gpxe/spi.h>
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#include <gpxe/nvo.h>
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#include <gpxe/if_ether.h>
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/**************************************************************************
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*
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* Constants and macros
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*
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**************************************************************************
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*/
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/* Board IDs. Early boards have no board_type, (e.g. EF1002 and 401/403)
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* But newer boards are getting bigger...
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*/
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typedef enum {
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EFAB_BOARD_INVALID = 0, /* Early boards do not have board rev. info. */
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EFAB_BOARD_SFE4001 = 1,
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EFAB_BOARD_SFE4002 = 2,
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EFAB_BOARD_SFE4003 = 3,
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/* Insert new types before here */
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EFAB_BOARD_MAX
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} efab_board_type;
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/* PHY types. */
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typedef enum {
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PHY_TYPE_AUTO = 0, /* on development board detect between CX4 & alaska */
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PHY_TYPE_CX4_RTMR = 1,
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PHY_TYPE_1GIG_ALASKA = 2,
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PHY_TYPE_10XPRESS = 3,
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PHY_TYPE_XFP = 4,
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PHY_TYPE_CX4 = 5,
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PHY_TYPE_PM8358 = 6,
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} phy_type_t;
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/**************************************************************************
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*
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* Hardware data structures and sizing
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*
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**************************************************************************
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*/
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#define dma_addr_t unsigned long
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typedef efab_qword_t falcon_rx_desc_t;
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typedef efab_qword_t falcon_tx_desc_t;
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typedef efab_qword_t falcon_event_t;
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#define EFAB_BUF_ALIGN 4096
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#define EFAB_RXD_SIZE 512
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#define EFAB_TXD_SIZE 512
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#define EFAB_EVQ_SIZE 512
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#define EFAB_NUM_RX_DESC 16
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#define EFAB_RX_BUF_SIZE 1600
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/**************************************************************************
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*
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* Data structures
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*
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**************************************************************************
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*/
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struct efab_nic;
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/* A buffer table allocation backing a tx dma, rx dma or eventq */
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struct efab_special_buffer {
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dma_addr_t dma_addr;
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int id;
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};
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/* A TX queue */
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struct efab_tx_queue {
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/* The hardware ring */
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falcon_tx_desc_t *ring;
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/* The software ring storing io_buffers. */
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struct io_buffer *buf[EFAB_TXD_SIZE];
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/* The buffer table reservation pushed to hardware */
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struct efab_special_buffer entry;
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/* Software descriptor write ptr */
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unsigned int write_ptr;
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/* Hardware descriptor read ptr */
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unsigned int read_ptr;
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};
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/* An RX queue */
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struct efab_rx_queue {
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/* The hardware ring */
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falcon_rx_desc_t *ring;
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/* The software ring storing io_buffers */
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struct io_buffer *buf[EFAB_NUM_RX_DESC];
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/* The buffer table reservation pushed to hardware */
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struct efab_special_buffer entry;
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/* Descriptor write ptr, into both the hardware and software rings */
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unsigned int write_ptr;
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/* Hardware completion ptr */
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unsigned int read_ptr;
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};
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/* An event queue */
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struct efab_ev_queue {
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/* The hardware ring to push to hardware.
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* Must be the first entry in the structure */
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falcon_event_t *ring;
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/* The buffer table reservation pushed to hardware */
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struct efab_special_buffer entry;
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/* Pointers into the ring */
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unsigned int read_ptr;
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};
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struct efab_mac_operations {
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int ( * init ) ( struct efab_nic *efab );
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};
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struct efab_phy_operations {
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int ( * init ) ( struct efab_nic *efab );
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unsigned int mmds;
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};
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struct efab_board_operations {
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int ( * init ) ( struct efab_nic *efab );
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void ( * fini ) ( struct efab_nic *efab );
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};
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struct efab_nic {
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struct net_device *netdev;
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int pci_revision;
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int is_asic;
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/* I2C bit-bashed interface */
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struct i2c_bit_basher i2c_bb;
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/** SPI bus and devices, and the user visible NVO area */
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struct spi_bus spi_bus;
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struct spi_device spi_flash;
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struct spi_device spi_eeprom;
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struct spi_device *spi;
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struct nvo_block nvo;
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/** Board, MAC, and PHY operations tables */
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struct efab_board_operations *board_op;
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struct efab_mac_operations *mac_op;
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struct efab_phy_operations *phy_op;
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/* PHY and board types */
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int phy_addr;
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int phy_type;
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int phy_10g;
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int board_type;
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/** Memory and IO base */
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void *membase;
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unsigned int iobase;
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/* Buffer table allocation head */
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int buffer_head;
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/* Queues */
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struct efab_rx_queue rx_queue;
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struct efab_tx_queue tx_queue;
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struct efab_ev_queue ev_queue;
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/** MAC address */
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uint8_t mac_addr[ETH_ALEN];
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/** GMII link options */
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unsigned int link_options;
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/** Link status */
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int link_up;
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/** INT_REG_KER */
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efab_oword_t int_ker __attribute__ (( aligned ( 16 ) ));
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};
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#endif /* EFAB_NIC_H */
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