mirror of https://github.com/ipxe/ipxe.git
259 lines
6.2 KiB
C
259 lines
6.2 KiB
C
#ifndef _IPXE_SPI_H
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#define _IPXE_SPI_H
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/** @file
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*
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* SPI interface
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/nvs.h>
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/**
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* @defgroup spicmds SPI commands
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* @{
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*/
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/** Write status register */
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#define SPI_WRSR 0x01
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/** Write data to memory array */
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#define SPI_WRITE 0x02
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/** Read data from memory array */
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#define SPI_READ 0x03
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/** Reset write enable latch */
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#define SPI_WRDI 0x04
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/** Read status register */
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#define SPI_RDSR 0x05
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/** Set write enable latch */
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#define SPI_WREN 0x06
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/**
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* @defgroup atmelcmds Atmel-specific SPI commands
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* @{
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*/
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/** Erase one sector in memory array (Not supported on all devices) */
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#define ATMEL_SECTOR_ERASE 0x52
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/** Erase all sections in memory array (Not supported on all devices) */
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#define ATMEL_CHIP_ERASE 0x62
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/** Read manufacturer and product ID (Not supported on all devices) */
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#define ATMEL_RDID 0x15
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/** @} */
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/** @} */
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/**
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* @defgroup spistatus SPI status register bits (not present on all devices)
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* @{
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*/
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/** Write-protect pin enabled */
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#define SPI_STATUS_WPEN 0x80
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/** Block protection bit 2 */
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#define SPI_STATUS_BP2 0x10
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/** Block protection bit 1 */
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#define SPI_STATUS_BP1 0x08
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/** Block protection bit 0 */
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#define SPI_STATUS_BP0 0x04
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/** State of the write enable latch */
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#define SPI_STATUS_WEN 0x02
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/** Device busy flag */
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#define SPI_STATUS_NRDY 0x01
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/** @} */
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/**
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* An SPI device
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*
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* This data structure represents a physical SPI device attached to an
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* SPI bus.
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*/
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struct spi_device {
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/** NVS device */
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struct nvs_device nvs;
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/** SPI bus to which device is attached */
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struct spi_bus *bus;
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/** Slave number */
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unsigned int slave;
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/** Command length, in bits */
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unsigned int command_len;
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/** Address length, in bits */
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unsigned int address_len;
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/** Address is munged
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*
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* Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
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* use bit 3 of the command byte as address bit A8, rather
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* than having a two-byte address. If this flag is set, then
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* commands should be munged in this way.
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*/
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unsigned int munge_address : 1;
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};
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/**
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* SPI magic autodetection address length
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*
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* Set @c spi_device::address_len to @c SPI_AUTODETECT_ADDRESS_LEN if
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* the address length should be autodetected.
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*/
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#define SPI_AUTODETECT_ADDRESS_LEN 0
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static inline __attribute__ (( always_inline )) struct spi_device *
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nvs_to_spi ( struct nvs_device *nvs ) {
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return container_of ( nvs, struct spi_device, nvs );
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}
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/**
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* An SPI bus
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*
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* This data structure represents an SPI bus controller capable of
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* issuing commands to attached SPI devices.
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*/
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struct spi_bus {
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/** SPI interface mode
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*
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* This is the bitwise OR of zero or more of @c SPI_MODE_CPHA
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* and @c SPI_MODE_CPOL. It is also the number conventionally
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* used to describe the SPI interface mode. For example, SPI
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* mode 1 is the mode in which CPOL=0 and CPHA=1, which
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* therefore corresponds to a mode value of (0|SPI_MODE_CPHA)
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* which, happily, equals 1.
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*/
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unsigned int mode;
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/**
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* Read/write data via SPI bus
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*
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* @v bus SPI bus
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* @v device SPI device
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* @v command Command
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* @v address Address to read/write (<0 for no address)
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* @v data_out TX data buffer (or NULL)
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* @v data_in RX data buffer (or NULL)
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* @v len Length of data buffer(s)
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*
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* This issues the specified command and optional address to
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* the SPI device, then reads and/or writes data to/from the
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* data buffers.
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*/
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int ( * rw ) ( struct spi_bus *bus, struct spi_device *device,
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unsigned int command, int address,
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const void *data_out, void *data_in, size_t len );
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};
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/** Clock phase (CPHA) mode bit
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*
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* Phase 0 is sample on rising edge, shift data on falling edge.
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*
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* Phase 1 is shift data on rising edge, sample data on falling edge.
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*/
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#define SPI_MODE_CPHA 0x01
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/** Clock polarity (CPOL) mode bit
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*
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* This bit reflects the idle state of the clock line (SCLK).
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*/
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#define SPI_MODE_CPOL 0x02
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/** Slave select polarity mode bit
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*
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* This bit reflects that active state of the slave select lines. It
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* is not part of the normal SPI mode number (which covers only @c
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* SPI_MODE_CPOL and @c SPI_MODE_CPHA), but is included here for
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* convenience.
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*/
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#define SPI_MODE_SSPOL 0x10
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/** Microwire-compatible mode
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*
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* This is SPI mode 1 (i.e. CPOL=0, CPHA=1), and is compatible with
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* the original Microwire protocol.
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*/
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#define SPI_MODE_MICROWIRE 1
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/** Microwire/Plus-compatible mode
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*
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* This is SPI mode 0 (i.e. CPOL=0, CPHA=0), and is compatible with
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* the Microwire/Plus protocol
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*/
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#define SPI_MODE_MICROWIRE_PLUS 0
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/** Threewire-compatible mode
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*
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* This mode is compatible with Atmel's series of "three-wire"
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* interfaces.
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*/
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#define SPI_MODE_THREEWIRE ( SPI_MODE_MICROWIRE_PLUS | SPI_MODE_SSPOL )
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extern int spi_read ( struct nvs_device *nvs, unsigned int address,
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void *data, size_t len );
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extern int spi_write ( struct nvs_device *nvs, unsigned int address,
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const void *data, size_t len );
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/**
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* @defgroup spidevs SPI device types
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* @{
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*/
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static inline __attribute__ (( always_inline )) void
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init_spi ( struct spi_device *device ) {
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device->nvs.word_len_log2 = 0;
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device->command_len = 8,
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device->nvs.read = spi_read;
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device->nvs.write = spi_write;
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}
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/** Atmel AT25F1024 serial flash */
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static inline __attribute__ (( always_inline )) void
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init_at25f1024 ( struct spi_device *device ) {
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device->address_len = 24;
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device->nvs.size = ( 128 * 1024 );
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device->nvs.block_size = 256;
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init_spi ( device );
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}
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/** Atmel 25040 serial EEPROM */
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static inline __attribute__ (( always_inline )) void
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init_at25040 ( struct spi_device *device ) {
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device->address_len = 8;
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device->munge_address = 1;
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device->nvs.size = 512;
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device->nvs.block_size = 8;
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init_spi ( device );
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}
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/** ST M25P32 serial flash */
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static inline __attribute__ (( always_inline )) void
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init_m25p32 ( struct spi_device *device ) {
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device->address_len = 24;
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device->nvs.size = ( 4 * 1024 * 1024 );
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device->nvs.block_size = 256;
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init_spi ( device );
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}
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/** Microchip 25XX640 serial EEPROM */
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static inline __attribute__ (( always_inline )) void
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init_mc25xx640 ( struct spi_device *device ) {
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device->address_len = 16;
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device->nvs.size = ( 8 * 1024 );
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device->nvs.block_size = 32;
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init_spi ( device );
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}
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/** @} */
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#endif /* _IPXE_SPI_H */
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