mirror of https://github.com/ipxe/ipxe.git
314 lines
8.4 KiB
C
314 lines
8.4 KiB
C
/** @file
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*
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* Marvell AQtion family network card driver, hardware-specific functions.
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*
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* Copyright(C) 2017-2024 Marvell
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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FILE_LICENCE ( BSD2 );
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#include <errno.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <byteswap.h>
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#include <ipxe/pci.h>
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#include "aqc1xx.h"
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#include "atl_hw.h"
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#include <compiler.h>
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int atl_hw_reset_flb_ ( struct atl_nic *nic ) {
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uint32_t val;
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int k = 0;
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ATL_WRITE_REG ( ATL_GLB_CTRL2_MBOX_ERR_UP_RUN_STALL, ATL_GLB_CTRL2 );
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mdelay ( ATL_DELAY_50_MNS );
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/* Cleanup SPI */
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val = ATL_READ_REG ( ATL_GLB_NVR_PROV4 );
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ATL_WRITE_REG ( val | ATL_GBL_NVR_PROV4_RESET, ATL_GLB_NVR_PROV4 );
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ATL_WRITE_REG( ( ATL_READ_REG ( ATL_GLB_STD_CTRL ) &
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~ATL_GLB_CTRL_RST_DIS ) | ATL_GLB_STD_CTRL_RESET,
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ATL_GLB_STD_CTRL );
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/* Kickstart MAC */
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ATL_WRITE_REG ( ATL_GLB_CTRL2_FW_RESET, ATL_GLB_CTRL2 );
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ATL_WRITE_REG ( ATL_MIF_PWR_GATING_EN_CTRL_RESET,
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ATL_MIF_PWR_GATING_EN_CTRL );
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ATL_WRITE_REG ( ATL_GEN_PROV9_ENABLE, ATL_GEN_PROV9 );
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/* Reset SPI again because of possible interrupted SPI burst */
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val = ATL_READ_REG ( ATL_GLB_NVR_PROV4 );
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ATL_WRITE_REG ( val | ATL_GBL_NVR_PROV4_RESET, ATL_GLB_NVR_PROV4 );
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mdelay ( ATL_DELAY_10_MNS );
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/* Clear SPI reset state */
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ATL_WRITE_REG ( val & ~ATL_GBL_NVR_PROV4_RESET, ATL_GLB_NVR_PROV4 );
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/* MAC Kickstart */
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ATL_WRITE_REG ( ATL_GLB_CTRL2_MAC_KICK_START, ATL_GLB_CTRL2 );
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for (k = 0; k < 1000; k++) {
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uint32_t flb_status = ATL_READ_REG ( ATL_MPI_DAISY_CHAIN_STS );
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flb_status = flb_status & FLB_LOAD_STS;
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if ( flb_status )
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break;
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mdelay ( ATL_DELAY_10_MNS );
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}
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if ( k == 1000 ) {
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DBGC (nic, "MAC kickstart failed\n" );
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return -EIO;
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}
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/* FW reset */
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ATL_WRITE_REG ( ATL_GLB_CTRL2_FW_RESET, ATL_GLB_CTRL2 );
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mdelay ( ATL_DELAY_50_MNS );
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ATL_WRITE_REG ( ATL_GBL_MCP_SEM1_RELEASE, ATL_GLB_MCP_SEM1 );
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/* Global software reset*/
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ATL_WRITE_REG ( ATL_READ_REG ( ATL_RX_CTRL ) &
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~ATL_RX_CTRL_RST_DIS, ATL_RX_CTRL );
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ATL_WRITE_REG ( ATL_READ_REG ( ATL_TX_CTRL ) &
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~ATL_TX_CTRL_RST_DIS, ATL_TX_CTRL );
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ATL_WRITE_REG ( ATL_READ_REG ( ATL_MAC_PHY_CTRL ) &
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~ATL_MAC_PHY_CTRL_RST_DIS, ATL_MAC_PHY_CTRL );
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ATL_WRITE_REG ( ( ATL_READ_REG ( ATL_GLB_STD_CTRL ) &
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~ATL_GLB_CTRL_RST_DIS ) | ATL_GLB_STD_CTRL_RESET,
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ATL_GLB_STD_CTRL );
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for (k = 0; k < 1000; k++) {
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u32 fw_state = ATL_READ_REG ( ATL_FW_VER );
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if ( fw_state )
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break;
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mdelay ( ATL_DELAY_10_MNS );
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}
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if ( k == 1000 ) {
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DBGC ( nic, "FW kickstart failed\n" );
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return -EIO;
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}
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/* Old FW requires fixed delay after init */
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mdelay ( ATL_DELAY_15_MNS );
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return 0;
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}
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int atl_hw_reset_rbl_ ( struct atl_nic *nic ) {
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uint32_t val, rbl_status;
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int k;
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ATL_WRITE_REG ( ATL_GLB_CTRL2_MBOX_ERR_UP_RUN_STALL, ATL_GLB_CTRL2 );
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ATL_WRITE_REG ( ATL_GBL_MCP_SEM1_RELEASE, ATL_GLB_MCP_SEM1 );
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ATL_WRITE_REG ( ATL_MIF_PWR_GATING_EN_CTRL_RESET,
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ATL_MIF_PWR_GATING_EN_CTRL );
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/* Alter RBL status */
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ATL_WRITE_REG ( POISON_SIGN, ATL_MPI_BOOT_EXIT_CODE );
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/* Cleanup SPI */
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val = ATL_READ_REG ( ATL_GLB_NVR_PROV4 );
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ATL_WRITE_REG ( val | ATL_GBL_NVR_PROV4_RESET, ATL_GLB_NVR_PROV4 );
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/* Global software reset*/
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ATL_WRITE_REG ( ATL_READ_REG ( ATL_RX_CTRL ) & ~ATL_RX_CTRL_RST_DIS,
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ATL_RX_CTRL );
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ATL_WRITE_REG ( ATL_READ_REG ( ATL_TX_CTRL ) & ~ATL_TX_CTRL_RST_DIS,
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ATL_TX_CTRL );
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ATL_WRITE_REG ( ATL_READ_REG ( ATL_MAC_PHY_CTRL ) &
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~ATL_MAC_PHY_CTRL_RST_DIS, ATL_MAC_PHY_CTRL );
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ATL_WRITE_REG ( ( ATL_READ_REG ( ATL_GLB_STD_CTRL ) &
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~ATL_GLB_CTRL_RST_DIS ) | ATL_GLB_STD_CTRL_RESET,
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ATL_GLB_STD_CTRL );
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ATL_WRITE_REG ( ATL_GLB_CTRL2_MBOX_ERR_UP_RUN_NORMAL, ATL_GLB_CTRL2 );
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/* Wait for RBL boot */
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for ( k = 0; k < 1000; k++ ) {
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rbl_status = ATL_READ_REG ( ATL_MPI_BOOT_EXIT_CODE ) & 0xFFFF;
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if ( rbl_status && rbl_status != POISON_SIGN )
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break;
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mdelay ( ATL_DELAY_10_MNS );
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}
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if ( !rbl_status || rbl_status == POISON_SIGN ) {
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DBGC ( nic, "RBL Restart failed\n" );
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return -EIO;
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}
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if ( rbl_status == FW_NOT_SUPPORT )
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return -ENOTSUP;
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for ( k = 0; k < 1000; k++ ) {
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u32 fw_state = ATL_READ_REG ( ATL_FW_VER );
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if ( fw_state )
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break;
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mdelay ( ATL_DELAY_10_MNS );
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}
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if ( k == 1000 ) {
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DBGC ( nic, "FW kickstart failed\n" );
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return -EIO;
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}
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/* Old FW requires fixed delay after init */
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mdelay ( ATL_DELAY_15_MNS );
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return 0;
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}
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int atl_hw_reset ( struct atl_nic *nic ) {
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uint32_t boot_exit_code = 0;
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uint32_t k;
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int rbl_enabled;
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uint32_t fw_ver;
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uint32_t sem_timeout;
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for ( k = 0; k < 1000; ++k ) {
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uint32_t flb_status = ATL_READ_REG ( ATL_MPI_DAISY_CHAIN_STS );
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boot_exit_code = ATL_READ_REG ( ATL_MPI_BOOT_EXIT_CODE );
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if ( flb_status != ATL_MPI_DAISY_CHAIN_STS_ERROR_STATUS ||
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boot_exit_code != 0 )
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break;
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}
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if ( k == 1000 ) {
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DBGC ( nic, "Neither RBL nor FLB firmware started\n" );
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return -ENOTSUP;
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}
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rbl_enabled = ( boot_exit_code != 0 );
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fw_ver = ATL_READ_REG ( ATL_FW_VER );
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if ( ( ( fw_ver >> 24 ) & 0xFF ) >= 4 ) {
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sem_timeout = ATL_READ_REG ( ATL_SEM_TIMEOUT );
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if ( sem_timeout > ATL_SEM_MAX_TIMEOUT )
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sem_timeout = ATL_SEM_MAX_TIMEOUT;
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for ( k = 0; k < sem_timeout; ++k ) {
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if ( ATL_READ_REG ( ATL_GLB_MCP_SEM4 ) )
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break;
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mdelay ( ATL_DELAY_1_MNS );
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}
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for ( k = 0; k < sem_timeout; ++k ) {
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if ( ATL_READ_REG ( ATL_GLB_MCP_SEM5 ) )
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break;
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mdelay ( ATL_DELAY_1_MNS );
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}
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}
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if ( rbl_enabled )
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return atl_hw_reset_rbl_ ( nic );
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else
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return atl_hw_reset_flb_ ( nic );
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}
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int atl_hw_start ( struct atl_nic *nic ) {
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ATL_WRITE_REG ( ATL_LINK_ADV_AUTONEG, ATL_LINK_ADV );
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return 0;
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}
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int atl_hw_stop ( struct atl_nic *nic ) {
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ATL_WRITE_REG ( ATL_SHUT_LINK, ATL_LINK_ADV );
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return 0;
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}
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int atl_hw_get_link ( struct atl_nic *nic ) {
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return ( ATL_READ_REG ( ATL_LINK_ST) & ATL_LINK_ADV_AUTONEG ) != 0;
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}
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int atl_hw_read_mem ( struct atl_nic *nic, uint32_t addr, uint32_t *buffer,
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uint32_t size ) {
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uint32_t i;
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for ( i = 0; i < 100; ++i ) {
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if ( ATL_READ_REG( ATL_SEM_RAM ) )
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break;
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mdelay ( ATL_DELAY_1_MNS );
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}
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if ( i == 100 ) {
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DBGC ( nic, "Semaphore Register not set\n" );
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return -EIO;
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}
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ATL_WRITE_REG ( addr, ATL_MBOX_CTRL3 );
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for ( i = 0; i < size; ++i, addr += 4 ) {
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uint32_t j;
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ATL_WRITE_REG ( ATL_MBOX_CTRL1_START_MBOX_OPT, ATL_MBOX_CTRL1 );
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for ( j = 0; j < 10000; ++j ) {
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if ( ATL_READ_REG (ATL_MBOX_CTRL3 ) != addr )
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break;
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udelay ( ATL_DELAY_10_MNS );
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}
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if ( j == 10000 ) {
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DBGC ( nic, "Reading from CTRL3 Register Failed\n" );
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return -EIO;
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}
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buffer[i] = ATL_READ_REG ( ATL_MBOX_CTRL5 );
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}
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ATL_WRITE_REG( ATL_SEM_RAM_RESET, ATL_SEM_RAM );
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return 0;
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}
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int atl_hw_get_mac ( struct atl_nic *nic, uint8_t *mac ) {
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uint32_t mac_addr[2] = {0};
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int err = 0;
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uint32_t efuse_addr = ATL_READ_REG ( ATL_GLB_MCP_SP26 );
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if ( efuse_addr != 0) {
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uint32_t mac_efuse_addr = efuse_addr + 40 * sizeof ( uint32_t );
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err = atl_hw_read_mem ( nic, mac_efuse_addr, mac_addr, 2 );
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if ( err != 0 )
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return err;
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mac_addr[0] = cpu_to_be32 ( mac_addr[0] );
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mac_addr[1] = cpu_to_be32 ( mac_addr[1] );
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memcpy ( mac, ( uint8_t * )mac_addr, ATL_MAC_ADDRESS_SIZE );
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}
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return 0;
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}
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struct atl_hw_ops atl_hw = {
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.reset = atl_hw_reset,
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.start = atl_hw_start,
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.stop = atl_hw_stop,
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.get_link = atl_hw_get_link,
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.get_mac = atl_hw_get_mac,
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};
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