mirror of https://github.com/ipxe/ipxe.git
700 lines
17 KiB
C
700 lines
17 KiB
C
/* natsemi.c - gPXE driver for the NatSemi DP8381x series. */
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/*
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natsemi.c: An Etherboot driver for the NatSemi DP8381x series.
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Copyright (C) 2001 Entity Cyber, Inc.
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This development of this Etherboot driver was funded by
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Sicom Systems: http://www.sicompos.com/
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Author: Marty Connor (mdc@thinguin.org)
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Adapted from a Linux driver which was written by Donald Becker
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This software may be used and distributed according to the terms
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of the GNU Public License (GPL), incorporated herein by reference.
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Original Copyright Notice:
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Written/copyright 1999-2001 by Donald Becker.
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This software may be used and distributed according to the terms of
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the GNU General Public License (GPL), incorporated herein by reference.
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Drivers based on or derived from this code fall under the GPL and must
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retain the authorship, copyright and license notice. This file is not
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a complete program and may only be used when the entire operating
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system is licensed under the GPL. License for under other terms may be
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available. Contact the original author for details.
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The original author may be reached as becker@scyld.com, or at
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Scyld Computing Corporation
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410 Severn Ave., Suite 210
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Annapolis MD 21403
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Support information and updates available at
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http://www.scyld.com/network/netsemi.html
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References:
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http://www.scyld.com/expert/100mbps.html
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http://www.scyld.com/expert/NWay.html
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Datasheet is available from:
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http://www.national.com/pf/DP/DP83815.html
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*/
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/* Revision History */
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/*
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02 JUL 2007 Udayan Kumar 1.2 ported the driver from etherboot to gPXE API.
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Fully rewritten,adapting the old driver.
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Added a circular buffer for transmit and receive.
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transmit routine will not wait for transmission to finish.
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poll routine deals with it.
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13 Dec 2003 timlegge 1.1 Enabled Multicast Support
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29 May 2001 mdc 1.0
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Initial Release. Tested with Netgear FA311 and FA312 boards
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*/
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#include <stdint.h>
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#include <pic8259.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <io.h>
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#include <errno.h>
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#include <timer.h>
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#include <byteswap.h>
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#include <gpxe/pci.h>
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#include <gpxe/if_ether.h>
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#include <gpxe/ethernet.h>
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#include <gpxe/iobuf.h>
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#include <gpxe/netdevice.h>
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#include <gpxe/spi_bit.h>
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#include <gpxe/threewire.h>
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#include <gpxe/nvo.h>
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#define TX_RING_SIZE 4
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#define NUM_RX_DESC 4
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#define RX_BUF_SIZE 1536
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#define OWN 0x80000000
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#define DSIZE 0x00000FFF
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#define CRC_SIZE 4
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struct natsemi_tx {
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uint32_t link;
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uint32_t cmdsts;
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uint32_t bufptr;
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};
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struct natsemi_rx {
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uint32_t link;
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uint32_t cmdsts;
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uint32_t bufptr;
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};
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struct natsemi_nic {
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unsigned short ioaddr;
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unsigned short tx_cur;
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unsigned short tx_dirty;
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unsigned short rx_cur;
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struct natsemi_tx tx[TX_RING_SIZE];
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struct natsemi_rx rx[NUM_RX_DESC];
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/* need to add iobuf as we cannot free iobuf->data in close without this
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* alternatively substracting sizeof(head) and sizeof(list_head) can also
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* give the same.
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*/
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struct io_buffer *iobuf[NUM_RX_DESC];
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/* netdev_tx_complete needs pointer to the iobuf of the data so as to free
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* it from the memory.
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*/
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struct io_buffer *tx_iobuf[TX_RING_SIZE];
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struct spi_bit_basher spibit;
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struct spi_device eeprom;
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struct nvo_block nvo;
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};
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/* NATSEMI: Offsets to the device registers.
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* Unlike software-only systems, device drivers interact with complex hardware.
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* It's not useful to define symbolic names for every register bit in the
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* device.
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*/
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enum register_offsets {
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ChipCmd = 0x00,
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ChipConfig = 0x04,
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EECtrl = 0x08,
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PCIBusCfg = 0x0C,
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IntrStatus = 0x10,
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IntrMask = 0x14,
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IntrEnable = 0x18,
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TxRingPtr = 0x20,
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TxConfig = 0x24,
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RxRingPtr = 0x30,
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RxConfig = 0x34,
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ClkRun = 0x3C,
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WOLCmd = 0x40,
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PauseCmd = 0x44,
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RxFilterAddr = 0x48,
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RxFilterData = 0x4C,
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BootRomAddr = 0x50,
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BootRomData = 0x54,
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SiliconRev = 0x58,
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StatsCtrl = 0x5C,
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StatsData = 0x60,
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RxPktErrs = 0x60,
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RxMissed = 0x68,
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RxCRCErrs = 0x64,
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PCIPM = 0x44,
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PhyStatus = 0xC0,
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MIntrCtrl = 0xC4,
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MIntrStatus = 0xC8,
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/* These are from the spec, around page 78... on a separate table.
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*/
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PGSEL = 0xCC,
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PMDCSR = 0xE4,
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TSTDAT = 0xFC,
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DSPCFG = 0xF4,
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SDCFG = 0x8C,
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BasicControl = 0x80,
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BasicStatus = 0x84
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};
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/* Bit in ChipCmd.
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*/
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enum ChipCmdBits {
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ChipReset = 0x100,
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RxReset = 0x20,
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TxReset = 0x10,
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RxOff = 0x08,
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RxOn = 0x04,
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TxOff = 0x02,
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TxOn = 0x01
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};
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/* Bits in the RxMode register.
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*/
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enum rx_mode_bits {
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0xC0000000,
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AcceptMulticast = 0x00200000,
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AcceptAllMulticast = 0x20000000,
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AcceptAllPhys = 0x10000000,
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AcceptMyPhys = 0x08000000,
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RxFilterEnable = 0x80000000
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};
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/* Bits in network_desc.status
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*/
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enum desc_status_bits {
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DescOwn = 0x80000000,
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DescMore = 0x40000000,
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DescIntr = 0x20000000,
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DescNoCRC = 0x10000000,
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DescPktOK = 0x08000000,
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RxTooLong = 0x00400000
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};
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/*Bits in Interrupt Mask register
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*/
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enum Intr_mask_register_bits {
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RxOk = 0x001,
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RxErr = 0x004,
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TxOk = 0x040,
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TxErr = 0x100
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};
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/* EEPROM access , values are devices specific
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*/
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#define EE_CS 0x08 /* EEPROM chip select */
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#define EE_SK 0x04 /* EEPROM shift clock */
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#define EE_DI 0x01 /* Data in */
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#define EE_DO 0x02 /* Data out */
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/* Offsets within EEPROM (these are word offsets)
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*/
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#define EE_MAC 7
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#define EE_REG EECtrl
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static uint32_t SavedClkRun;
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static const uint8_t nat_ee_bits[] = {
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[SPI_BIT_SCLK] = EE_SK,
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[SPI_BIT_MOSI] = EE_DI,
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[SPI_BIT_MISO] = EE_DO,
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[SPI_BIT_SS(0)] = EE_CS,
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};
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static int nat_spi_read_bit ( struct bit_basher *basher,
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unsigned int bit_id ) {
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struct natsemi_nic *nat = container_of ( basher, struct natsemi_nic,
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spibit.basher );
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uint8_t mask = nat_ee_bits[bit_id];
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uint8_t eereg;
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eereg = inb ( nat->ioaddr + EE_REG);
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return ( eereg & mask );
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}
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static void nat_spi_write_bit ( struct bit_basher *basher,
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unsigned int bit_id, unsigned long data ) {
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struct natsemi_nic *nat = container_of ( basher, struct natsemi_nic,
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spibit.basher );
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uint8_t mask = nat_ee_bits[bit_id];
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uint8_t eereg;
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eereg = inb ( nat->ioaddr + EE_REG );
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eereg &= ~mask;
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eereg |= ( data & mask );
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outb ( eereg, nat->ioaddr + EE_REG);
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}
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static struct bit_basher_operations nat_basher_ops = {
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.read = nat_spi_read_bit,
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.write = nat_spi_write_bit,
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};
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/* It looks that this portion of EEPROM can be used for
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* non-volatile stored options. Data sheet does not talk about this region.
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* Currently it is not working. But with some efforts it can.
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*/
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static struct nvo_fragment nat_nvo_fragments[] = {
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{ 0x0c, 0x68 },
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{ 0, 0 }
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};
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/*
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* Set up for EEPROM access
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*
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* @v NAT NATSEMI NIC
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*/
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void nat_init_eeprom ( struct natsemi_nic *nat ) {
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/* Initialise three-wire bus
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*/
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nat->spibit.basher.op = &nat_basher_ops;
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nat->spibit.bus.mode = SPI_MODE_THREEWIRE;
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nat->spibit.endianness = SPI_BIT_LITTLE_ENDIAN;
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init_spi_bit_basher ( &nat->spibit );
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/*natsemi DP 83815 only supports at93c46
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*/
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init_at93c46 ( &nat->eeprom, 16 );
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nat->eeprom.bus = &nat->spibit.bus;
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nat->nvo.nvs = &nat->eeprom.nvs;
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nat->nvo.fragments = nat_nvo_fragments;
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}
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/*
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* Reset NIC
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*
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* @v NATSEMI NIC
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*
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* Issues a hardware reset and waits for the reset to complete.
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*/
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static void nat_reset ( struct natsemi_nic *nat ) {
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int i;
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/* Reset chip
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*/
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outl ( ChipReset, nat->ioaddr + ChipCmd );
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mdelay ( 10 );
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nat->tx_dirty=0;
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nat->tx_cur=0;
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for(i=0;i<TX_RING_SIZE;i++) {
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nat->tx[i].link=0;
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nat->tx[i].cmdsts=0;
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nat->tx[i].bufptr=0;
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}
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nat->rx_cur = 0;
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outl(virt_to_bus(&nat->tx[0]),nat->ioaddr+TxRingPtr);
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outl(virt_to_bus(&nat->rx[0]), nat->ioaddr + RxRingPtr);
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outl(TxOff|RxOff, nat->ioaddr + ChipCmd);
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/* Restore PME enable bit
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*/
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outl(SavedClkRun, nat->ioaddr + ClkRun);
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}
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/*
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* Open NIC
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*
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* @v netdev Net device
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* @ret rc Return status code
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*/
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static int nat_open ( struct net_device *netdev ) {
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struct natsemi_nic *nat = netdev->priv;
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int i;
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uint32_t tx_config,rx_config;
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/* Disable PME:
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* The PME bit is initialized from the EEPROM contents.
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* PCI cards probably have PME disabled, but motherboard
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* implementations may have PME set to enable WakeOnLan.
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* With PME set the chip will scan incoming packets but
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* nothing will be written to memory.
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*/
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SavedClkRun = inl(nat->ioaddr + ClkRun);
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outl(SavedClkRun & ~0x100, nat->ioaddr + ClkRun);
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/* Setting up Mac address in the NIC
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*/
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for ( i = 0 ; i < ETH_ALEN ; i+=2 ) {
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outl(i,nat->ioaddr+RxFilterAddr);
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outw ( netdev->ll_addr[i] + (netdev->ll_addr[i+1]<<8),
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nat->ioaddr +RxFilterData);
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}
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/*Set up the Tx Ring
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*/
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nat->tx_cur=0;
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nat->tx_dirty=0;
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for (i=0;i<TX_RING_SIZE;i++) {
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nat->tx[i].link = virt_to_bus((i+1 < TX_RING_SIZE) ? &nat->tx[i+1] : &nat->tx[0]);
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nat->tx[i].cmdsts = 0;
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nat->tx[i].bufptr = 0;
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}
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/* Set up RX ring
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*/
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nat->rx_cur=0;
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for (i=0;i<NUM_RX_DESC;i++) {
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nat->iobuf[i] = alloc_iob ( RX_BUF_SIZE );
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if (!nat->iobuf[i])
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goto memory_alloc_err;
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nat->rx[i].link = virt_to_bus((i+1 < NUM_RX_DESC) ? &nat->rx[i+1] : &nat->rx[0]);
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nat->rx[i].cmdsts = RX_BUF_SIZE;
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nat->rx[i].bufptr = virt_to_bus(nat->iobuf[i]->data);
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}
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/* load Receive Descriptor Register
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*/
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outl(virt_to_bus(&nat->rx[0]), nat->ioaddr + RxRingPtr);
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DBG("Natsemi Rx descriptor loaded with: %X\n",
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(unsigned int)inl(nat->ioaddr+RxRingPtr));
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/* setup Tx ring
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*/
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outl(virt_to_bus(&nat->tx[0]),nat->ioaddr+TxRingPtr);
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DBG("Natsemi Tx descriptor loaded with: %X\n",
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(unsigned int)inl(nat->ioaddr+TxRingPtr));
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/* Enables RX
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*/
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outl(RxFilterEnable|AcceptBroadcast|AcceptAllMulticast|AcceptMyPhys,
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nat->ioaddr+RxFilterAddr);
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/* Initialize other registers.
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* Configure the PCI bus bursts and FIFO thresholds.
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* Configure for standard, in-spec Ethernet.
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*/
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if (inl(nat->ioaddr + ChipConfig) & 0x20000000) { /* Full duplex */
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tx_config = 0xD0801002;
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rx_config = 0x10000020;
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} else {
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tx_config = 0x10801002;
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rx_config = 0x0020;
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}
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outl(tx_config, nat->ioaddr + TxConfig);
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outl(rx_config, nat->ioaddr + RxConfig);
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/*start the receiver
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*/
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outl(RxOn, nat->ioaddr + ChipCmd);
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/* mask the interrupts. note interrupt is not enabled here
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*/
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return 0;
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memory_alloc_err:
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/* this block frees the previously allocated buffers
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* if memory for all the buffers is not available
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*/
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i=0;
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while(nat->rx[i].cmdsts == RX_BUF_SIZE) {
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free_iob(nat->iobuf[i]);
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i++;
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}
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return -ENOMEM;
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}
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/**
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* Close NIC
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*
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* @v netdev Net device
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*/
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static void nat_close ( struct net_device *netdev ) {
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struct natsemi_nic *nat = netdev->priv;
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int i;
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/* Reset the hardware to disable everything in one go
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*/
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nat_reset ( nat );
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/* Free RX ring
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*/
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for (i=0;i<NUM_RX_DESC;i++) {
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free_iob( nat->iobuf[i] );
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}
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}
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/**
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* Transmit packet
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*
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* @v netdev Network device
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* @v iobuf I/O buffer
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* @ret rc Return status code
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*/
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static int nat_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
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struct natsemi_nic *nat = netdev->priv;
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/* check for space in TX ring
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*/
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if (nat->tx[nat->tx_cur].cmdsts !=0) {
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DBG( "TX overflow\n" );
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return -ENOBUFS;
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}
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/* to be used in netdev_tx_complete
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*/
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nat->tx_iobuf[nat->tx_cur]=iobuf;
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/* Pad and align packet has not been used because its not required here
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* iob_pad ( iobuf, ETH_ZLEN ); can be used to achieve it
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*/
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/* Add to TX ring
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*/
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DBG ( "TX id %d at %lx+%x\n", nat->tx_cur,
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virt_to_bus ( &iobuf->data ), iob_len ( iobuf ) );
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nat->tx[nat->tx_cur].bufptr = virt_to_bus(iobuf->data);
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nat->tx[nat->tx_cur].cmdsts= iob_len(iobuf)|OWN;
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/* increment the circular buffer pointer to the next buffer location
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*/
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nat->tx_cur=(nat->tx_cur+1) % TX_RING_SIZE;
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/*start the transmitter
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*/
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outl(TxOn, nat->ioaddr + ChipCmd);
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return 0;
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}
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/**
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* Poll for received packets
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*
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* @v netdev Network device
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* @v rx_quota Maximum number of packets to receive
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*/
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static void nat_poll ( struct net_device *netdev) {
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struct natsemi_nic *nat = netdev->priv;
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unsigned int status;
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unsigned int rx_status;
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unsigned int intr_status;
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unsigned int rx_len;
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struct io_buffer *rx_iob;
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int i;
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/* read the interrupt register
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*/
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intr_status=inl(nat->ioaddr+IntrStatus);
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if(!intr_status)
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goto end;
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/* check the status of packets given to card for transmission
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*/
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DBG("Intr status %X\n",intr_status);
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i=nat->tx_dirty;
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while(i!=nat->tx_cur) {
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status=nat->tx[nat->tx_dirty].cmdsts;
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DBG("value of tx_dirty = %d tx_cur=%d status=%X\n",
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nat->tx_dirty,nat->tx_cur,status);
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/* check if current packet has been transmitted or not
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*/
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if(status & OWN)
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break;
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/* Check if any errors in transmission
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*/
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if (! (status & DescPktOK)) {
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DBG("Error in sending Packet status:%X\n",
|
|
(unsigned int)status);
|
|
netdev_tx_complete_err(netdev,nat->tx_iobuf[nat->tx_dirty],-EINVAL);
|
|
} else {
|
|
DBG("Success in transmitting Packet\n");
|
|
netdev_tx_complete(netdev,nat->tx_iobuf[nat->tx_dirty]);
|
|
}
|
|
/* setting cmdsts zero, indicating that it can be reused
|
|
*/
|
|
nat->tx[nat->tx_dirty].cmdsts=0;
|
|
nat->tx_dirty=(nat->tx_dirty +1) % TX_RING_SIZE;
|
|
i=(i+1) % TX_RING_SIZE;
|
|
}
|
|
|
|
/* Handle received packets
|
|
*/
|
|
rx_status=(unsigned int)nat->rx[nat->rx_cur].cmdsts;
|
|
while ((rx_status & OWN)) {
|
|
rx_len= (rx_status & DSIZE) - CRC_SIZE;
|
|
/*check for the corrupt packet
|
|
*/
|
|
if((rx_status & (DescMore|DescPktOK|RxTooLong)) != DescPktOK) {
|
|
DBG("natsemi_poll: Corrupted packet received, "
|
|
"buffer status = %X ^ %X \n",rx_status,
|
|
(unsigned int) nat->rx[nat->rx_cur].cmdsts);
|
|
netdev_rx_err(netdev,NULL,-EINVAL);
|
|
} else {
|
|
rx_iob = alloc_iob(rx_len);
|
|
if(!rx_iob)
|
|
/* leave packet for next call to poll
|
|
*/
|
|
goto end;
|
|
memcpy(iob_put(rx_iob,rx_len),
|
|
nat->iobuf[nat->rx_cur]->data,rx_len);
|
|
DBG("received packet\n");
|
|
/* add to the receive queue.
|
|
*/
|
|
netdev_rx(netdev,rx_iob);
|
|
}
|
|
nat->rx[nat->rx_cur].cmdsts = RX_BUF_SIZE;
|
|
nat->rx_cur=(nat->rx_cur+1) % NUM_RX_DESC;
|
|
rx_status=nat->rx[nat->rx_cur].cmdsts;
|
|
}
|
|
end:
|
|
/* re-enable the potentially idle receive state machine
|
|
*/
|
|
outl(RxOn, nat->ioaddr + ChipCmd);
|
|
}
|
|
|
|
/**
|
|
* Enable/disable interrupts
|
|
*
|
|
* @v netdev Network device
|
|
* @v enable Interrupts should be enabled
|
|
*/
|
|
static void nat_irq ( struct net_device *netdev, int enable ) {
|
|
struct natsemi_nic *nat= netdev->priv;
|
|
|
|
outl((enable?(RxOk|RxErr|TxOk|TxErr):0),
|
|
nat->ioaddr + IntrMask);
|
|
outl((enable ? 1:0),nat->ioaddr +IntrEnable);
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/** natsemi net device operations */
|
|
static struct net_device_operations nat_operations = {
|
|
.open = nat_open,
|
|
.close = nat_close,
|
|
.transmit = nat_transmit,
|
|
.poll = nat_poll,
|
|
.irq = nat_irq,
|
|
};
|
|
|
|
/*
|
|
* Probe PCI device
|
|
*
|
|
* @v pci PCI device
|
|
* @v id PCI ID
|
|
* @ret rc Return status code
|
|
*/
|
|
static int nat_probe ( struct pci_device *pci,
|
|
const struct pci_device_id *id __unused ) {
|
|
struct net_device *netdev;
|
|
struct natsemi_nic *nat = NULL;
|
|
int rc;
|
|
int i;
|
|
uint8_t ll_addr_encoded[MAX_LL_ADDR_LEN];
|
|
uint8_t last=0;
|
|
uint8_t last1=0;
|
|
uint8_t prev_bytes[2];
|
|
|
|
/* Allocate net device
|
|
*/
|
|
netdev = alloc_etherdev ( sizeof ( *nat ) );
|
|
if ( ! netdev )
|
|
return -ENOMEM;
|
|
netdev_init(netdev,&nat_operations);
|
|
nat = netdev->priv;
|
|
pci_set_drvdata ( pci, netdev );
|
|
netdev->dev = &pci->dev;
|
|
memset ( nat, 0, sizeof ( *nat ) );
|
|
nat->ioaddr = pci->ioaddr;
|
|
|
|
/* Fix up PCI device
|
|
*/
|
|
adjust_pci_device ( pci );
|
|
|
|
/* Reset the NIC, set up EEPROM access and read MAC address
|
|
*/
|
|
nat_reset ( nat );
|
|
nat_init_eeprom ( nat );
|
|
nvs_read ( &nat->eeprom.nvs, EE_MAC-1, prev_bytes, 1);
|
|
nvs_read ( &nat->eeprom.nvs, EE_MAC, ll_addr_encoded, ETH_ALEN );
|
|
/* decoding the MAC address read from NVS
|
|
* and save it in netdev->ll_addr
|
|
*/
|
|
last=prev_bytes[1]>>7;
|
|
for ( i = 0 ; i < ETH_ALEN ; i++) {
|
|
last1=ll_addr_encoded[i]>>7;
|
|
netdev->ll_addr[i]=ll_addr_encoded[i]<<1|last;
|
|
last=last1;
|
|
}
|
|
|
|
/* Register network device
|
|
*/
|
|
if ( ( rc = register_netdev ( netdev ) ) != 0 )
|
|
goto err_register_netdev;
|
|
|
|
return 0;
|
|
|
|
err_register_netdev:
|
|
/* Disable NIC
|
|
*/
|
|
nat_reset ( nat );
|
|
/* Free net device
|
|
*/
|
|
netdev_put ( netdev );
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* Remove PCI device
|
|
*
|
|
* @v pci PCI device
|
|
*/
|
|
static void nat_remove ( struct pci_device *pci ) {
|
|
struct net_device *netdev = pci_get_drvdata ( pci );
|
|
struct natsemi_nic *nat = netdev->priv;
|
|
|
|
if ( nat->nvo.nvs )
|
|
nvo_unregister ( &nat->nvo );
|
|
|
|
unregister_netdev ( netdev );
|
|
nat_reset ( nat );
|
|
netdev_put ( netdev );
|
|
}
|
|
|
|
static struct pci_device_id natsemi_nics[] = {
|
|
PCI_ROM(0x100b, 0x0020, "dp83815", "DP83815"),
|
|
};
|
|
|
|
struct pci_driver natsemi_driver __pci_driver = {
|
|
.ids = natsemi_nics,
|
|
.id_count = ( sizeof ( natsemi_nics ) / sizeof ( natsemi_nics[0] ) ),
|
|
.probe = nat_probe,
|
|
.remove = nat_remove,
|
|
};
|