mirror of https://github.com/ipxe/ipxe.git
724 lines
21 KiB
C
724 lines
21 KiB
C
#ifdef ALLMULTI
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#error multicast support is not yet implemented
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#endif
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/*
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DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00
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This driver was ported from Marty Connor's Tulip Etherboot driver.
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Thanks Marty Connor (mdc@etherboot.org)
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This davicom etherboot driver supports DM9009/DM9102/DM9102A/
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DM9102A+DM9801/DM9102A+DM9802 NICs.
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This software may be used and distributed according to the terms
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of the GNU Public License, incorporated herein by reference.
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*/
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/*********************************************************************/
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/* Revision History */
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/*********************************************************************/
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/*
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19 OCT 2000 Sten 1.00
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Different half and full duplex mode
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Do the different programming for DM9801/DM9802
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12 OCT 2000 Sten 0.90
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This driver was ported from tulip driver and it
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has the following difference.
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Changed symbol tulip/TULIP to davicom/DAVICOM
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Deleted some code that did not use in this driver.
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Used chain-strcture to replace ring structure
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for both TX/RX descriptor.
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Allocated two tx descriptor.
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According current media mode to set operating
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register(CR6)
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*/
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/*********************************************************************/
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/* Declarations */
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/*********************************************************************/
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#include "etherboot.h"
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#include "nic.h"
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#include "pci.h"
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#undef DAVICOM_DEBUG
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#undef DAVICOM_DEBUG_WHERE
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#define TX_TIME_OUT 2*TICKS_PER_SEC
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typedef unsigned char u8;
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typedef signed char s8;
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typedef unsigned short u16;
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typedef signed short s16;
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typedef unsigned int u32;
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typedef signed int s32;
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/* Register offsets for davicom device */
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enum davicom_offsets {
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CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
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CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
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CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
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};
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/* EEPROM Address width definitions */
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#define EEPROM_ADDRLEN 6
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#define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */
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/* Used to be 128, but we only need to read enough to get the MAC
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address at bytes 20..25 */
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/* Data Read from the EEPROM */
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static unsigned char ee_data[EEPROM_SIZE];
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_WRITE_CMD (5 << addr_len)
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#define EE_READ_CMD (6 << addr_len)
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#define EE_ERASE_CMD (7 << addr_len)
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/* EEPROM_Ctrl bits. */
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#define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
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#define EE_CS 0x01 /* EEPROM chip select. */
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#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
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#define EE_WRITE_0 0x01
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#define EE_WRITE_1 0x05
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#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
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#define EE_ENB (0x4800 | EE_CS)
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/* Sten 10/11 for phyxcer */
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#define PHY_DATA_0 0x0
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#define PHY_DATA_1 0x20000
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#define MDCLKH 0x10000
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/* Delay between EEPROM clock transitions. Even at 33Mhz current PCI
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implementations don't overrun the EEPROM clock. We add a bus
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turn-around to insure that this remains true. */
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#define eeprom_delay() inl(ee_addr)
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/* helpful macro if on a big_endian machine for changing byte order.
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not strictly needed on Intel
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Already defined in Etherboot includes
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#define le16_to_cpu(val) (val)
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*/
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/* transmit and receive descriptor format */
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struct txdesc {
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volatile unsigned long status; /* owner, status */
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unsigned long buf1sz:11, /* size of buffer 1 */
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buf2sz:11, /* size of buffer 2 */
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control:10; /* control bits */
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const unsigned char *buf1addr; /* buffer 1 address */
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const unsigned char *buf2addr; /* buffer 2 address */
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};
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struct rxdesc {
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volatile unsigned long status; /* owner, status */
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unsigned long buf1sz:11, /* size of buffer 1 */
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buf2sz:11, /* size of buffer 2 */
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control:10; /* control bits */
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unsigned char *buf1addr; /* buffer 1 address */
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unsigned char *buf2addr; /* buffer 2 address */
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};
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/* Size of transmit and receive buffers */
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#define BUFLEN 1536
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/*********************************************************************/
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/* Global Storage */
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/*********************************************************************/
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static struct nic_operations davicom_operations;
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static struct pci_driver davicom_driver;
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/* PCI Bus parameters */
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static unsigned short vendor, dev_id;
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static unsigned long ioaddr;
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/* Note: transmit and receive buffers must be longword aligned and
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longword divisable */
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/* transmit descriptor and buffer */
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#define NTXD 2
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static struct txdesc txd[NTXD] __attribute__ ((aligned(4)));
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static unsigned char txb[BUFLEN] __attribute__ ((aligned(4)));
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/* receive descriptor(s) and buffer(s) */
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#define NRXD 4
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static struct rxdesc rxd[NRXD] __attribute__ ((aligned(4)));
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static unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4)));
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static int rxd_tail;
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static int TxPtr;
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/*********************************************************************/
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/* Function Prototypes */
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/*********************************************************************/
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static void whereami(const char *str);
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static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
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static int davicom_probe(struct dev *dev);
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static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */
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static void davicom_reset(struct nic *nic);
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static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
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unsigned int s, const char *p);
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static int davicom_poll(struct nic *nic, int retrieve);
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static void davicom_disable(struct nic *nic);
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#ifdef DAVICOM_DEBUG
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static void davicom_more(void);
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#endif /* DAVICOM_DEBUG */
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static void davicom_wait(unsigned int nticks);
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static int phy_read(int);
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static void phy_write(int, u16);
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static void phy_write_1bit(u32, u32);
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static int phy_read_1bit(u32);
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static void davicom_media_chk(struct nic *);
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/*********************************************************************/
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/* Utility Routines */
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/*********************************************************************/
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static inline void whereami(const char *str)
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{
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printf("%s\n", str);
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/* sleep(2); */
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}
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#ifdef DAVICOM_DEBUG
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static void davicom_more()
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{
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printf("\n\n-- more --");
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while (!iskey())
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/* wait */;
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getchar();
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printf("\n\n");
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}
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#endif /* DAVICOM_DEBUG */
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static void davicom_wait(unsigned int nticks)
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{
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unsigned int to = currticks() + nticks;
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while (currticks() < to)
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/* wait */ ;
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}
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/*********************************************************************/
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/* For DAVICOM phyxcer register by MII interface */
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/*********************************************************************/
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/*
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Read a word data from phy register
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*/
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static int phy_read(int location)
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{
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int i, phy_addr=1;
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u16 phy_data;
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u32 io_dcr9;
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whereami("phy_read\n");
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io_dcr9 = ioaddr + CSR9;
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/* Send 33 synchronization clock to Phy controller */
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for (i=0; i<34; i++)
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phy_write_1bit(io_dcr9, PHY_DATA_1);
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/* Send start command(01) to Phy */
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phy_write_1bit(io_dcr9, PHY_DATA_0);
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phy_write_1bit(io_dcr9, PHY_DATA_1);
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/* Send read command(10) to Phy */
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phy_write_1bit(io_dcr9, PHY_DATA_1);
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phy_write_1bit(io_dcr9, PHY_DATA_0);
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/* Send Phy addres */
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for (i=0x10; i>0; i=i>>1)
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phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
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/* Send register addres */
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for (i=0x10; i>0; i=i>>1)
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phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
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/* Skip transition state */
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phy_read_1bit(io_dcr9);
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/* read 16bit data */
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for (phy_data=0, i=0; i<16; i++) {
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phy_data<<=1;
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phy_data|=phy_read_1bit(io_dcr9);
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}
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return phy_data;
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}
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/*
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Write a word to Phy register
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*/
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static void phy_write(int location, u16 phy_data)
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{
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u16 i, phy_addr=1;
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u32 io_dcr9;
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whereami("phy_write\n");
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io_dcr9 = ioaddr + CSR9;
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/* Send 33 synchronization clock to Phy controller */
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for (i=0; i<34; i++)
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phy_write_1bit(io_dcr9, PHY_DATA_1);
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/* Send start command(01) to Phy */
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phy_write_1bit(io_dcr9, PHY_DATA_0);
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phy_write_1bit(io_dcr9, PHY_DATA_1);
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/* Send write command(01) to Phy */
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phy_write_1bit(io_dcr9, PHY_DATA_0);
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phy_write_1bit(io_dcr9, PHY_DATA_1);
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/* Send Phy addres */
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for (i=0x10; i>0; i=i>>1)
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phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
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/* Send register addres */
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for (i=0x10; i>0; i=i>>1)
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phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
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/* written trasnition */
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phy_write_1bit(io_dcr9, PHY_DATA_1);
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phy_write_1bit(io_dcr9, PHY_DATA_0);
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/* Write a word data to PHY controller */
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for (i=0x8000; i>0; i>>=1)
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phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0);
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}
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/*
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Write one bit data to Phy Controller
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*/
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static void phy_write_1bit(u32 ee_addr, u32 phy_data)
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{
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whereami("phy_write_1bit\n");
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outl(phy_data, ee_addr); /* MII Clock Low */
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eeprom_delay();
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outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */
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eeprom_delay();
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outl(phy_data, ee_addr); /* MII Clock Low */
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eeprom_delay();
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}
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/*
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Read one bit phy data from PHY controller
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*/
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static int phy_read_1bit(u32 ee_addr)
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{
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int phy_data;
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whereami("phy_read_1bit\n");
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outl(0x50000, ee_addr);
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eeprom_delay();
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phy_data=(inl(ee_addr)>>19) & 0x1;
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outl(0x40000, ee_addr);
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eeprom_delay();
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return phy_data;
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}
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/*
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DM9801/DM9802 present check and program
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*/
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static void HPNA_process(void)
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{
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if ( (phy_read(3) & 0xfff0) == 0xb900 ) {
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if ( phy_read(31) == 0x4404 ) {
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/* DM9801 present */
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if (phy_read(3) == 0xb901)
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phy_write(16, 0x5); /* DM9801 E4 */
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else
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phy_write(16, 0x1005); /* DM9801 E3 and others */
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phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000);
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} else {
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/* DM9802 present */
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phy_write(16, 0x5);
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phy_write(25, (phy_read(25) & 0xff00) + 2);
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}
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}
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}
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/*
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Sense media mode and set CR6
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*/
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static void davicom_media_chk(struct nic * nic __unused)
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{
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unsigned long to, csr6;
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csr6 = 0x00200000; /* SF */
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outl(csr6, ioaddr + CSR6);
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#define PCI_DEVICE_ID_DM9009 0x9009
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if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) {
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/* Set to 10BaseT mode for DM9009 */
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phy_write(0, 0);
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} else {
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/* For DM9102/DM9102A */
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to = currticks() + 2 * TICKS_PER_SEC;
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while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to))
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/* wait */ ;
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if ( (phy_read(1) & 0x24) == 0x24 ) {
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if (phy_read(17) & 0xa000)
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csr6 |= 0x00000200; /* Full Duplex mode */
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} else
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csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */
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}
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/* set the chip's operating mode */
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outl(csr6, ioaddr + CSR6);
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/* DM9801/DM9802 present check & program */
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if (csr6 & 0x40000)
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HPNA_process();
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}
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/*********************************************************************/
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/* EEPROM Reading Code */
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/*********************************************************************/
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/* EEPROM routines adapted from the Linux Tulip Code */
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/* Reading a serial EEPROM is a "bit" grungy, but we work our way
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through:->.
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*/
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static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
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{
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int i;
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unsigned short retval = 0;
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long ee_addr = ioaddr + CSR9;
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int read_cmd = location | EE_READ_CMD;
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whereami("read_eeprom\n");
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outl(EE_ENB & ~EE_CS, ee_addr);
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outl(EE_ENB, ee_addr);
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/* Shift the read command bits out. */
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for (i = 4 + addr_len; i >= 0; i--) {
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short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
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outl(EE_ENB | dataval, ee_addr);
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eeprom_delay();
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outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
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eeprom_delay();
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}
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outl(EE_ENB, ee_addr);
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for (i = 16; i > 0; i--) {
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outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
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eeprom_delay();
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retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
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outl(EE_ENB, ee_addr);
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eeprom_delay();
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}
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|
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/* Terminate the EEPROM access. */
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outl(EE_ENB & ~EE_CS, ee_addr);
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return retval;
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}
|
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|
||
/*********************************************************************/
|
||
/* davicom_init_chain - setup the tx and rx descriptors */
|
||
/* Sten 10/9 */
|
||
/*********************************************************************/
|
||
static void davicom_init_chain(struct nic *nic)
|
||
{
|
||
int i;
|
||
|
||
/* setup the transmit descriptor */
|
||
/* Sten: Set 2 TX descriptor but use one TX buffer because
|
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it transmit a packet and wait complete every time. */
|
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for (i=0; i<NTXD; i++) {
|
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txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */
|
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txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */
|
||
txd[i].buf1sz = 0;
|
||
txd[i].buf2sz = 0;
|
||
txd[i].control = 0x184; /* Begin/End/Chain */
|
||
txd[i].status = 0x00000000; /* give ownership to Host */
|
||
}
|
||
|
||
/* construct perfect filter frame with mac address as first match
|
||
and broadcast address for all others */
|
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for (i=0; i<192; i++) txb[i] = 0xFF;
|
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txb[0] = nic->node_addr[0];
|
||
txb[1] = nic->node_addr[1];
|
||
txb[4] = nic->node_addr[2];
|
||
txb[5] = nic->node_addr[3];
|
||
txb[8] = nic->node_addr[4];
|
||
txb[9] = nic->node_addr[5];
|
||
|
||
/* setup receive descriptor */
|
||
for (i=0; i<NRXD; i++) {
|
||
rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
|
||
rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
|
||
rxd[i].buf1sz = BUFLEN;
|
||
rxd[i].buf2sz = 0; /* not used */
|
||
rxd[i].control = 0x4; /* Chain Structure */
|
||
rxd[i].status = 0x80000000; /* give ownership to device */
|
||
}
|
||
|
||
/* Chain the last descriptor to first */
|
||
txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
|
||
rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
|
||
TxPtr = 0;
|
||
rxd_tail = 0;
|
||
}
|
||
|
||
|
||
/*********************************************************************/
|
||
/* davicom_reset - Reset adapter */
|
||
/*********************************************************************/
|
||
static void davicom_reset(struct nic *nic)
|
||
{
|
||
unsigned long to;
|
||
|
||
whereami("davicom_reset\n");
|
||
|
||
/* Stop Tx and RX */
|
||
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
|
||
|
||
/* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
|
||
outl(0x00000001, ioaddr + CSR0);
|
||
|
||
davicom_wait(TICKS_PER_SEC);
|
||
|
||
/* TX/RX descriptor burst */
|
||
outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */
|
||
|
||
/* set up transmit and receive descriptors */
|
||
davicom_init_chain(nic); /* Sten 10/9 */
|
||
|
||
/* Point to receive descriptor */
|
||
outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
|
||
outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */
|
||
|
||
/* According phyxcer media mode to set CR6,
|
||
DM9102/A phyxcer can auto-detect media mode */
|
||
davicom_media_chk(nic);
|
||
|
||
/* Prepare Setup Frame Sten 10/9 */
|
||
txd[TxPtr].buf1sz = 192;
|
||
txd[TxPtr].control = 0x024; /* SF/CE */
|
||
txd[TxPtr].status = 0x80000000; /* Give ownership to device */
|
||
|
||
/* Start Tx */
|
||
outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
|
||
/* immediate transmit demand */
|
||
outl(0, ioaddr + CSR1);
|
||
|
||
to = currticks() + TX_TIME_OUT;
|
||
while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */
|
||
/* wait */ ;
|
||
|
||
if (currticks() >= to) {
|
||
printf ("TX Setup Timeout!\n");
|
||
}
|
||
/* Point to next TX descriptor */
|
||
TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
|
||
|
||
#ifdef DAVICOM_DEBUG
|
||
printf("txd.status = %X\n", txd.status);
|
||
printf("ticks = %d\n", currticks() - (to - TX_TIME_OUT));
|
||
davicom_more();
|
||
#endif
|
||
|
||
/* enable RX */
|
||
outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
|
||
/* immediate poll demand */
|
||
outl(0, ioaddr + CSR2);
|
||
}
|
||
|
||
|
||
/*********************************************************************/
|
||
/* eth_transmit - Transmit a frame */
|
||
/*********************************************************************/
|
||
static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
|
||
unsigned int s, const char *p)
|
||
{
|
||
unsigned long to;
|
||
|
||
whereami("davicom_transmit\n");
|
||
|
||
/* Stop Tx */
|
||
/* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */
|
||
|
||
/* setup ethernet header */
|
||
memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */
|
||
memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/
|
||
txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */
|
||
txb[ETH_ALEN*2+1] = t & 0xFF;
|
||
memcpy(&txb[ETH_HLEN], p, s); /* Frame data */
|
||
|
||
/* setup the transmit descriptor */
|
||
txd[TxPtr].buf1sz = ETH_HLEN+s;
|
||
txd[TxPtr].control = 0x00000184; /* LS+FS+CE */
|
||
txd[TxPtr].status = 0x80000000; /* give ownership to device */
|
||
|
||
/* immediate transmit demand */
|
||
outl(0, ioaddr + CSR1);
|
||
|
||
to = currticks() + TX_TIME_OUT;
|
||
while ((txd[TxPtr].status & 0x80000000) && (currticks() < to))
|
||
/* wait */ ;
|
||
|
||
if (currticks() >= to) {
|
||
printf ("TX Timeout!\n");
|
||
}
|
||
|
||
/* Point to next TX descriptor */
|
||
TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
|
||
|
||
}
|
||
|
||
/*********************************************************************/
|
||
/* eth_poll - Wait for a frame */
|
||
/*********************************************************************/
|
||
static int davicom_poll(struct nic *nic, int retrieve)
|
||
{
|
||
whereami("davicom_poll\n");
|
||
|
||
if (rxd[rxd_tail].status & 0x80000000)
|
||
return 0;
|
||
|
||
if ( ! retrieve ) return 1;
|
||
|
||
whereami("davicom_poll got one\n");
|
||
|
||
nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;
|
||
|
||
if( rxd[rxd_tail].status & 0x00008000){
|
||
rxd[rxd_tail].status = 0x80000000;
|
||
rxd_tail++;
|
||
if (rxd_tail == NRXD) rxd_tail = 0;
|
||
return 0;
|
||
}
|
||
|
||
/* copy packet to working buffer */
|
||
/* XXX - this copy could be avoided with a little more work
|
||
but for now we are content with it because the optimised
|
||
memcpy is quite fast */
|
||
|
||
memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen);
|
||
|
||
/* return the descriptor and buffer to receive ring */
|
||
rxd[rxd_tail].status = 0x80000000;
|
||
rxd_tail++;
|
||
if (rxd_tail == NRXD) rxd_tail = 0;
|
||
|
||
return 1;
|
||
}
|
||
|
||
/*********************************************************************/
|
||
/* eth_disable - Disable the interface */
|
||
/*********************************************************************/
|
||
static void davicom_disable ( struct nic *nic ) {
|
||
whereami("davicom_disable\n");
|
||
|
||
davicom_reset(nic);
|
||
|
||
/* disable interrupts */
|
||
outl(0x00000000, ioaddr + CSR7);
|
||
|
||
/* Stop the chip's Tx and Rx processes. */
|
||
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
|
||
|
||
/* Clear the missed-packet counter. */
|
||
(volatile unsigned long)inl(ioaddr + CSR8);
|
||
}
|
||
|
||
|
||
/*********************************************************************/
|
||
/* eth_irq - enable, disable and force interrupts */
|
||
/*********************************************************************/
|
||
static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
|
||
{
|
||
switch ( action ) {
|
||
case DISABLE :
|
||
break;
|
||
case ENABLE :
|
||
break;
|
||
case FORCE :
|
||
break;
|
||
}
|
||
}
|
||
|
||
|
||
/*********************************************************************/
|
||
/* eth_probe - Look for an adapter */
|
||
/*********************************************************************/
|
||
static int davicom_probe ( struct dev *dev ) {
|
||
struct nic *nic = nic_device ( dev );
|
||
struct pci_device *pci = pci_device ( dev );
|
||
unsigned int i;
|
||
|
||
whereami("davicom_probe\n");
|
||
|
||
if ( ! find_pci_device ( pci, &davicom_driver ) )
|
||
return 0;
|
||
|
||
if (pci->ioaddr == 0)
|
||
return 0;
|
||
|
||
vendor = pci->vendor;
|
||
dev_id = pci->dev_id;
|
||
ioaddr = pci->ioaddr;
|
||
|
||
nic->irqno = 0;
|
||
nic->ioaddr = pci->ioaddr;
|
||
|
||
/* wakeup chip */
|
||
pci_write_config_dword(pci, 0x40, 0x00000000);
|
||
|
||
/* Stop the chip's Tx and Rx processes. */
|
||
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
|
||
|
||
/* Clear the missed-packet counter. */
|
||
(volatile unsigned long)inl(ioaddr + CSR8);
|
||
|
||
/* Get MAC Address */
|
||
/* read EEPROM data */
|
||
for (i = 0; i < sizeof(ee_data)/2; i++)
|
||
((unsigned short *)ee_data)[i] =
|
||
le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN));
|
||
|
||
/* extract MAC address from EEPROM buffer */
|
||
for (i=0; i<ETH_ALEN; i++)
|
||
nic->node_addr[i] = ee_data[20+i];
|
||
|
||
printf("Davicom %! at ioaddr %#hX\n", nic->node_addr, ioaddr);
|
||
|
||
/* initialize device */
|
||
davicom_reset(nic);
|
||
nic->nic_op = &davicom_operations;
|
||
return 1;
|
||
}
|
||
|
||
static struct nic_operations davicom_operations = {
|
||
.connect = dummy_connect,
|
||
.poll = davicom_poll,
|
||
.transmit = davicom_transmit,
|
||
.irq = davicom_irq,
|
||
.disable = davicom_disable,
|
||
};
|
||
|
||
static struct pci_id davicom_nics[] = {
|
||
PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100"),
|
||
PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102"),
|
||
PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009"),
|
||
PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132"), /* Needs probably some fixing */
|
||
};
|
||
|
||
static struct pci_driver davicom_driver =
|
||
PCI_DRIVER ( "DAVICOM", davicom_nics, PCI_NO_CLASS );
|
||
|
||
BOOT_DRIVER ( "DAVICOM", davicom_probe );
|