opengnsys_ipxe/src/arch/riscv
Michael Brown 167a08f089 [crypto] Expose carry flag from big integer addition and subtraction
Expose the effective carry (or borrow) out flag from big integer
addition and subtraction, and use this to elide an explicit bit test
when performing x25519 reduction.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
2024-11-26 12:55:13 +00:00
..
core [riscv] Check if seed CSR is accessible from S-mode 2024-10-28 23:07:14 +00:00
include [crypto] Expose carry flag from big integer addition and subtraction 2024-11-26 12:55:13 +00:00
interface/sbi [sbi] Add support for running as a RISC-V SBI payload 2024-10-28 19:20:50 +00:00
prefix [sbi] Add support for running as a RISC-V SBI payload 2024-10-28 19:20:50 +00:00
scripts [sbi] Add support for running as a RISC-V SBI payload 2024-10-28 19:20:50 +00:00
Makefile [sbi] Add support for running as a RISC-V SBI payload 2024-10-28 19:20:50 +00:00
Makefile.efi [riscv] Add support for the RISC-V CPU architecture 2024-09-15 22:34:10 +01:00
Makefile.linux [riscv] Add support for the RISC-V CPU architecture 2024-09-15 22:34:10 +01:00
Makefile.sbi [sbi] Add support for running as a RISC-V SBI payload 2024-10-28 19:20:50 +00:00