mirror of https://github.com/ipxe/ipxe.git
1120 lines
31 KiB
C
1120 lines
31 KiB
C
#ifndef _INTELX_H
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#define _INTELX_H
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/** @file
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*
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* Intel 40 Gigabit Ethernet network card driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/if_ether.h>
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#include <ipxe/pcimsix.h>
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#include <ipxe/dma.h>
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struct intelxl_nic;
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/** BAR size */
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#define INTELXL_BAR_SIZE 0x200000
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/** Alignment
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*
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* No data structure requires greater than 256 byte alignment.
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*/
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#define INTELXL_ALIGN 256
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/******************************************************************************
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*
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* Admin queue
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*
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******************************************************************************
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*/
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/** PF Admin Command Queue register block */
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#define INTELXL_ADMIN_CMD 0x080000
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/** PF Admin Event Queue register block */
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#define INTELXL_ADMIN_EVT 0x080080
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/** Admin Queue Base Address Low Register (offset) */
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#define INTELXL_ADMIN_BAL 0x000
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/** Admin Queue Base Address High Register (offset) */
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#define INTELXL_ADMIN_BAH 0x100
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/** Admin Queue Length Register (offset) */
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#define INTELXL_ADMIN_LEN 0x200
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#define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) /**< Queue length */
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#define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL /**< Queue enable */
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/** Admin Queue Head Register (offset) */
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#define INTELXL_ADMIN_HEAD 0x300
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/** Admin Queue Tail Register (offset) */
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#define INTELXL_ADMIN_TAIL 0x400
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/** Admin queue register offsets
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*
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* The physical and virtual function register maps have no discernible
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* relationship.
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*/
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struct intelxl_admin_offsets {
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/** Base Address Low Register offset */
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unsigned int bal;
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/** Base Address High Register offset */
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unsigned int bah;
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/** Length Register offset */
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unsigned int len;
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/** Head Register offset */
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unsigned int head;
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/** Tail Register offset */
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unsigned int tail;
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};
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/** Admin queue data buffer command parameters */
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struct intelxl_admin_buffer_params {
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/** Reserved */
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uint8_t reserved[8];
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/** Buffer address high */
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uint32_t high;
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/** Buffer address low */
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uint32_t low;
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} __attribute__ (( packed ));
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/** Admin queue Get Version command */
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#define INTELXL_ADMIN_VERSION 0x0001
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/** Admin queue version number */
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struct intelxl_admin_version {
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/** Major version number */
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uint16_t major;
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/** Minor version number */
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uint16_t minor;
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} __attribute__ (( packed ));
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/** Admin queue Get Version command parameters */
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struct intelxl_admin_version_params {
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/** ROM version */
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uint32_t rom;
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/** Firmware build ID */
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uint32_t build;
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/** Firmware version */
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struct intelxl_admin_version firmware;
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/** API version */
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struct intelxl_admin_version api;
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} __attribute__ (( packed ));
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/** Admin queue Driver Version command */
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#define INTELXL_ADMIN_DRIVER 0x0002
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/** Admin queue Driver Version command parameters */
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struct intelxl_admin_driver_params {
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/** Driver version */
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uint8_t major;
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/** Minor version */
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uint8_t minor;
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/** Build version */
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uint8_t build;
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/** Sub-build version */
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uint8_t sub;
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/** Reserved */
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uint8_t reserved[4];
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/** Data buffer address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Admin queue Driver Version data buffer */
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struct intelxl_admin_driver_buffer {
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/** Driver name */
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char name[32];
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} __attribute__ (( packed ));
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/** Admin queue Shutdown command */
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#define INTELXL_ADMIN_SHUTDOWN 0x0003
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/** Admin queue Shutdown command parameters */
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struct intelxl_admin_shutdown_params {
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/** Driver unloading */
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uint8_t unloading;
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/** Reserved */
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uint8_t reserved[15];
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} __attribute__ (( packed ));
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/** Driver is unloading */
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#define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
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/** Admin queue Clear PXE Mode command */
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#define INTELXL_ADMIN_CLEAR_PXE 0x0110
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/** Admin queue Clear PXE Mode command parameters */
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struct intelxl_admin_clear_pxe_params {
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/** Magic value */
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uint8_t magic;
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/** Reserved */
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uint8_t reserved[15];
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} __attribute__ (( packed ));
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/** Clear PXE Mode magic value */
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#define INTELXL_ADMIN_CLEAR_PXE_MAGIC 0x02
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/** Admin queue Get Switch Configuration command */
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#define INTELXL_ADMIN_SWITCH 0x0200
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/** Switching element configuration */
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struct intelxl_admin_switch_config {
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/** Switching element type */
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uint8_t type;
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/** Revision */
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uint8_t revision;
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/** Switching element ID */
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uint16_t seid;
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/** Uplink switching element ID */
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uint16_t uplink;
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/** Downlink switching element ID */
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uint16_t downlink;
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/** Reserved */
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uint8_t reserved_b[3];
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/** Connection type */
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uint8_t connection;
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/** Reserved */
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uint8_t reserved_c[2];
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/** Element specific information */
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uint16_t info;
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} __attribute__ (( packed ));
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/** Virtual Station Inferface element type */
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#define INTELXL_ADMIN_SWITCH_TYPE_VSI 19
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/** Admin queue Get Switch Configuration command parameters */
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struct intelxl_admin_switch_params {
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/** Starting switching element identifier */
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uint16_t next;
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/** Reserved */
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uint8_t reserved[6];
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/** Data buffer address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Admin queue Get Switch Configuration data buffer */
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struct intelxl_admin_switch_buffer {
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/** Number of switching elements reported */
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uint16_t count;
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/** Total number of switching elements */
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uint16_t total;
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/** Reserved */
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uint8_t reserved_a[12];
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/** Switch configuration */
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struct intelxl_admin_switch_config cfg;
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} __attribute__ (( packed ));
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/** Admin queue Get VSI Parameters command */
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#define INTELXL_ADMIN_VSI 0x0212
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/** Admin queue Get VSI Parameters command parameters */
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struct intelxl_admin_vsi_params {
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/** VSI switching element ID */
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uint16_t vsi;
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/** Reserved */
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uint8_t reserved[6];
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/** Data buffer address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Admin queue Get VSI Parameters data buffer */
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struct intelxl_admin_vsi_buffer {
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/** Reserved */
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uint8_t reserved_a[30];
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/** Queue numbers */
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uint16_t queue[16];
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/** Reserved */
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uint8_t reserved_b[34];
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/** Queue set handles for each traffic class */
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uint16_t qset[8];
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/** Reserved */
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uint8_t reserved_c[16];
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} __attribute__ (( packed ));
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/** Admin queue Set VSI Promiscuous Modes command */
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#define INTELXL_ADMIN_PROMISC 0x0254
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/** Admin queue Set VSI Promiscuous Modes command parameters */
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struct intelxl_admin_promisc_params {
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/** Flags */
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uint16_t flags;
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/** Valid flags */
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uint16_t valid;
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/** VSI switching element ID */
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uint16_t vsi;
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/** Reserved */
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uint8_t reserved[10];
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} __attribute__ (( packed ));
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/** Promiscuous unicast mode */
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#define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
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/** Promiscuous multicast mode */
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#define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
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/** Promiscuous broadcast mode */
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#define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
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/** Promiscuous VLAN mode */
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#define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
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/** Admin queue Restart Autonegotiation command */
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#define INTELXL_ADMIN_AUTONEG 0x0605
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/** Admin queue Restart Autonegotiation command parameters */
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struct intelxl_admin_autoneg_params {
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/** Flags */
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uint8_t flags;
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/** Reserved */
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uint8_t reserved[15];
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} __attribute__ (( packed ));
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/** Restart autonegotiation */
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#define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
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/** Enable link */
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#define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
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/** Admin queue Get Link Status command */
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#define INTELXL_ADMIN_LINK 0x0607
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/** Admin queue Get Link Status command parameters */
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struct intelxl_admin_link_params {
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/** Link status notification */
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uint8_t notify;
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/** Reserved */
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uint8_t reserved_a;
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/** PHY type */
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uint8_t phy;
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/** Link speed */
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uint8_t speed;
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/** Link status */
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uint8_t status;
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/** Reserved */
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uint8_t reserved_b[11];
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} __attribute__ (( packed ));
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/** Notify driver of link status changes */
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#define INTELXL_ADMIN_LINK_NOTIFY 0x03
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/** Link is up */
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#define INTELXL_ADMIN_LINK_UP 0x01
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/** Admin queue Send Message to PF command */
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#define INTELXL_ADMIN_SEND_TO_PF 0x0801
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/** Admin queue Send Message to VF command */
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#define INTELXL_ADMIN_SEND_TO_VF 0x0802
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/** Admin Queue VF Reset opcode */
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#define INTELXL_ADMIN_VF_RESET 0x00000002
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/** Admin Queue VF Get Resources opcode */
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#define INTELXL_ADMIN_VF_GET_RESOURCES 0x00000003
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/** Admin Queue VF Get Resources data buffer */
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struct intelxl_admin_vf_get_resources_buffer {
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/** Reserved */
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uint8_t reserved_a[20];
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/** VSI switching element ID */
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uint16_t vsi;
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/** Reserved */
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uint8_t reserved_b[8];
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/** MAC address */
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uint8_t mac[ETH_ALEN];
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} __attribute__ (( packed ));
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/** Admin Queue VF Status Change Event opcode */
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#define INTELXL_ADMIN_VF_STATUS 0x00000011
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/** Link status change event type */
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#define INTELXL_ADMIN_VF_STATUS_LINK 0x00000001
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/** Link status change event data */
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struct intelxl_admin_vf_status_link {
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/** Link speed */
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uint32_t speed;
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/** Link status */
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uint8_t status;
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/** Reserved */
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uint8_t reserved[3];
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} __attribute__ (( packed ));
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/** Admin Queue VF Status Change Event data buffer */
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struct intelxl_admin_vf_status_buffer {
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/** Event type */
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uint32_t event;
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/** Event data */
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union {
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/** Link change event data */
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struct intelxl_admin_vf_status_link link;
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} data;
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/** Reserved */
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uint8_t reserved[4];
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} __attribute__ (( packed ));
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/** Admin Queue VF Configure Queues opcode */
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#define INTELXL_ADMIN_VF_CONFIGURE 0x00000006
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/** Admin Queue VF Configure Queues data buffer */
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struct intelxl_admin_vf_configure_buffer {
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/** VSI switching element ID */
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uint16_t vsi;
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/** Number of queue pairs */
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uint16_t count;
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/** Reserved */
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uint8_t reserved_a[4];
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/** Transmit queue */
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struct {
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/** VSI switching element ID */
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uint16_t vsi;
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/** Queue ID */
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uint16_t id;
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/** Queue count */
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uint16_t count;
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/** Reserved */
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uint8_t reserved_a[2];
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/** Base address */
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uint64_t base;
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/** Reserved */
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uint8_t reserved_b[8];
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} __attribute__ (( packed )) tx;
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/** Receive queue */
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struct {
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/** VSI switching element ID */
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uint16_t vsi;
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/** Queue ID */
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uint16_t id;
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/** Queue count */
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uint32_t count;
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/** Reserved */
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uint8_t reserved_a[4];
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/** Data buffer length */
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uint32_t len;
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/** Maximum frame size */
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uint32_t mfs;
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/** Reserved */
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uint8_t reserved_b[4];
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/** Base address */
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uint64_t base;
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/** Reserved */
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uint8_t reserved_c[8];
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} __attribute__ (( packed )) rx;
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/** Reserved
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*
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* This field exists only due to a bug in the PF driver's
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* message validation logic, which causes it to miscalculate
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* the expected message length.
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*/
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uint8_t reserved_b[64];
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} __attribute__ (( packed ));
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/** Admin Queue VF IRQ Map opcode */
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#define INTELXL_ADMIN_VF_IRQ_MAP 0x00000007
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/** Admin Queue VF IRQ Map data buffer */
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struct intelxl_admin_vf_irq_map_buffer {
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/** Number of interrupt vectors */
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uint16_t count;
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/** VSI switching element ID */
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uint16_t vsi;
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/** Interrupt vector ID */
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uint16_t vec;
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/** Receive queue bitmap */
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uint16_t rxmap;
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/** Transmit queue bitmap */
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uint16_t txmap;
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/** Receive interrupt throttling index */
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uint16_t rxitr;
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/** Transmit interrupt throttling index */
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uint16_t txitr;
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/** Reserved
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*
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* This field exists only due to a bug in the PF driver's
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* message validation logic, which causes it to miscalculate
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* the expected message length.
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*/
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uint8_t reserved[12];
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} __attribute__ (( packed ));
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/** Admin Queue VF Enable Queues opcode */
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#define INTELXL_ADMIN_VF_ENABLE 0x00000008
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/** Admin Queue VF Disable Queues opcode */
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#define INTELXL_ADMIN_VF_DISABLE 0x00000009
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/** Admin Queue VF Enable/Disable Queues data buffer */
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struct intelxl_admin_vf_queues_buffer {
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/** VSI switching element ID */
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uint16_t vsi;
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/** Reserved */
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uint8_t reserved[2];
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/** Receive queue bitmask */
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uint32_t rx;
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/** Transmit queue bitmask */
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uint32_t tx;
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} __attribute__ (( packed ));
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/** Admin Queue VF Configure Promiscuous Mode opcode */
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#define INTELXL_ADMIN_VF_PROMISC 0x0000000e
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/** Admin Queue VF Configure Promiscuous Mode data buffer */
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struct intelxl_admin_vf_promisc_buffer {
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/** VSI switching element ID */
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uint16_t vsi;
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/** Flags */
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uint16_t flags;
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} __attribute__ (( packed ));
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/** Admin queue command parameters */
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union intelxl_admin_params {
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/** Additional data buffer command parameters */
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struct intelxl_admin_buffer_params buffer;
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/** Get Version command parameters */
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struct intelxl_admin_version_params version;
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/** Driver Version command parameters */
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struct intelxl_admin_driver_params driver;
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/** Shutdown command parameters */
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struct intelxl_admin_shutdown_params shutdown;
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/** Clear PXE Mode command parameters */
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struct intelxl_admin_clear_pxe_params pxe;
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/** Get Switch Configuration command parameters */
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struct intelxl_admin_switch_params sw;
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/** Get VSI Parameters command parameters */
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struct intelxl_admin_vsi_params vsi;
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/** Set VSI Promiscuous Modes command parameters */
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struct intelxl_admin_promisc_params promisc;
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/** Restart Autonegotiation command parameters */
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struct intelxl_admin_autoneg_params autoneg;
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/** Get Link Status command parameters */
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struct intelxl_admin_link_params link;
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} __attribute__ (( packed ));
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/** Admin queue data buffer */
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union intelxl_admin_buffer {
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/** Driver Version data buffer */
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struct intelxl_admin_driver_buffer driver;
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/** Get Switch Configuration data buffer */
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struct intelxl_admin_switch_buffer sw;
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/** Get VSI Parameters data buffer */
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struct intelxl_admin_vsi_buffer vsi;
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/** VF Get Resources data buffer */
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struct intelxl_admin_vf_get_resources_buffer res;
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/** VF Status Change Event data buffer */
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struct intelxl_admin_vf_status_buffer stat;
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/** VF Configure Queues data buffer */
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struct intelxl_admin_vf_configure_buffer cfg;
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/** VF Enable/Disable Queues data buffer */
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struct intelxl_admin_vf_queues_buffer queues;
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/** VF Configure Promiscuous Mode data buffer */
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struct intelxl_admin_vf_promisc_buffer promisc;
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/*** VF IRQ Map data buffer */
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struct intelxl_admin_vf_irq_map_buffer irq;
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/** Alignment padding */
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uint8_t pad[INTELXL_ALIGN];
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} __attribute__ (( packed ));
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/** Admin queue descriptor */
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struct intelxl_admin_descriptor {
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/** Flags */
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uint16_t flags;
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/** Opcode */
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uint16_t opcode;
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/** Data length */
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uint16_t len;
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/** Return value */
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uint16_t ret;
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/** Opaque cookie / VF opcode */
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union {
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/** Cookie */
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uint32_t cookie;
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/** VF opcode */
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uint32_t vopcode;
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};
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/** VF return value */
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int32_t vret;
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/** Parameters */
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union intelxl_admin_params params;
|
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} __attribute__ (( packed ));
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/** Admin descriptor done */
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#define INTELXL_ADMIN_FL_DD 0x0001
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/** Admin descriptor contains a completion */
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#define INTELXL_ADMIN_FL_CMP 0x0002
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|
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/** Admin descriptor completed in error */
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#define INTELXL_ADMIN_FL_ERR 0x0004
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|
|
|
/** Admin descriptor uses data buffer for command parameters */
|
|
#define INTELXL_ADMIN_FL_RD 0x0400
|
|
|
|
/** Admin descriptor uses data buffer */
|
|
#define INTELXL_ADMIN_FL_BUF 0x1000
|
|
|
|
/** Admin queue */
|
|
struct intelxl_admin {
|
|
/** Descriptors */
|
|
struct intelxl_admin_descriptor *desc;
|
|
/** Data buffers */
|
|
union intelxl_admin_buffer *buf;
|
|
/** DMA mapping */
|
|
struct dma_mapping map;
|
|
/** Queue index */
|
|
unsigned int index;
|
|
|
|
/** Register block base */
|
|
unsigned int base;
|
|
/** Register offsets */
|
|
const struct intelxl_admin_offsets *regs;
|
|
};
|
|
|
|
/**
|
|
* Initialise admin queue
|
|
*
|
|
* @v admin Admin queue
|
|
* @v base Register block base
|
|
* @v regs Register offsets
|
|
*/
|
|
static inline __attribute__ (( always_inline )) void
|
|
intelxl_init_admin ( struct intelxl_admin *admin, unsigned int base,
|
|
const struct intelxl_admin_offsets *regs ) {
|
|
|
|
admin->base = base;
|
|
admin->regs = regs;
|
|
}
|
|
|
|
/** Number of admin queue descriptors */
|
|
#define INTELXL_ADMIN_NUM_DESC 4
|
|
|
|
/** Maximum time to wait for an admin request to complete */
|
|
#define INTELXL_ADMIN_MAX_WAIT_MS 100
|
|
|
|
/** Admin queue API major version */
|
|
#define INTELXL_ADMIN_API_MAJOR 1
|
|
|
|
/******************************************************************************
|
|
*
|
|
* Transmit and receive queue context
|
|
*
|
|
******************************************************************************
|
|
*/
|
|
|
|
/** CMLAN Context Data Register */
|
|
#define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
|
|
|
|
/** CMLAN Context Control Register */
|
|
#define INTELXL_PFCM_LANCTXCTL 0x10c300
|
|
#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \
|
|
( (x) << 0 ) /**< Queue number */
|
|
#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \
|
|
( (x) << 12 ) /**< Sub-line */
|
|
#define INTELXL_PFCM_LANCTXCTL_TYPE(x) \
|
|
( (x) << 15 ) /**< Queue type */
|
|
#define INTELXL_PFCM_LANCTXCTL_TYPE_RX \
|
|
INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) /**< RX queue type */
|
|
#define INTELXL_PFCM_LANCTXCTL_TYPE_TX \
|
|
INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) /**< TX queue type */
|
|
#define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \
|
|
( (x) << 17 ) /**< Op code */
|
|
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \
|
|
INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) /**< Read context */
|
|
#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \
|
|
INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) /**< Write context */
|
|
|
|
/** CMLAN Context Status Register */
|
|
#define INTELXL_PFCM_LANCTXSTAT 0x10c380
|
|
#define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL /**< Complete */
|
|
|
|
/** Queue context line */
|
|
struct intelxl_context_line {
|
|
/** Raw data */
|
|
uint32_t raw[4];
|
|
} __attribute__ (( packed ));
|
|
|
|
/** Transmit queue context */
|
|
struct intelxl_context_tx {
|
|
/** Head pointer */
|
|
uint16_t head;
|
|
/** Flags */
|
|
uint16_t flags;
|
|
/** Base address */
|
|
uint64_t base;
|
|
/** Reserved */
|
|
uint8_t reserved_a[8];
|
|
/** Queue count */
|
|
uint16_t count;
|
|
/** Reserved */
|
|
uint8_t reserved_b[100];
|
|
/** Queue set */
|
|
uint16_t qset;
|
|
/** Reserved */
|
|
uint8_t reserved_c[4];
|
|
} __attribute__ (( packed ));
|
|
|
|
/** New transmit queue context */
|
|
#define INTELXL_CTX_TX_FL_NEW 0x4000
|
|
|
|
/** Transmit queue base address */
|
|
#define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 )
|
|
|
|
/** Transmit queue count */
|
|
#define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 )
|
|
|
|
/** Transmit queue set */
|
|
#define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 )
|
|
|
|
/** Receive queue context */
|
|
struct intelxl_context_rx {
|
|
/** Head pointer */
|
|
uint16_t head;
|
|
/** Reserved */
|
|
uint8_t reserved_a[2];
|
|
/** Base address and queue count */
|
|
uint64_t base_count;
|
|
/** Data buffer length */
|
|
uint16_t len;
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Reserved */
|
|
uint8_t reserved_b[7];
|
|
/** Maximum frame size */
|
|
uint16_t mfs;
|
|
/** Reserved */
|
|
uint8_t reserved_c[8];
|
|
} __attribute__ (( packed ));
|
|
|
|
/** Receive queue base address and queue count */
|
|
#define INTELXL_CTX_RX_BASE_COUNT( base, count ) \
|
|
( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
|
|
|
|
/** Receive queue data buffer length */
|
|
#define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 )
|
|
|
|
/** Use 32-byte receive descriptors */
|
|
#define INTELXL_CTX_RX_FL_DSIZE 0x10
|
|
|
|
/** Strip CRC from received packets */
|
|
#define INTELXL_CTX_RX_FL_CRCSTRIP 0x20
|
|
|
|
/** Receive queue maximum frame size */
|
|
#define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 )
|
|
|
|
/** Maximum time to wait for a context operation to complete */
|
|
#define INTELXL_CTX_MAX_WAIT_MS 100
|
|
|
|
/** Time to wait for a queue to become enabled */
|
|
#define INTELXL_QUEUE_ENABLE_DELAY_US 20
|
|
|
|
/** Time to wait for a transmit queue to become pre-disabled */
|
|
#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
|
|
|
|
/** Maximum time to wait for a queue to become disabled */
|
|
#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
|
|
|
|
/******************************************************************************
|
|
*
|
|
* Transmit and receive descriptors
|
|
*
|
|
******************************************************************************
|
|
*/
|
|
|
|
/** Global Transmit Queue Head register */
|
|
#define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
|
|
|
|
/** Global Transmit Pre Queue Disable register */
|
|
#define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
|
|
#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \
|
|
( (x) << 0 ) /**< Queue index */
|
|
#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \
|
|
0x40000000UL /**< Set disable */
|
|
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \
|
|
0x80000000UL /**< Clear disable */
|
|
|
|
/** Global Transmit Queue register block */
|
|
#define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
|
|
|
|
/** Global Receive Queue register block */
|
|
#define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
|
|
|
|
/** Queue Enable Register (offset) */
|
|
#define INTELXL_QXX_ENA 0x0000
|
|
#define INTELXL_QXX_ENA_REQ 0x00000001UL /**< Enable request */
|
|
#define INTELXL_QXX_ENA_STAT 0x00000004UL /**< Enabled status */
|
|
|
|
/** Queue Control Register (offset) */
|
|
#define INTELXL_QXX_CTL 0x4000
|
|
#define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) /**< PF/VF queue */
|
|
#define INTELXL_QXX_CTL_PFVF_Q_PF \
|
|
INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) /**< PF queue */
|
|
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) /**< PF index */
|
|
|
|
/** Queue Tail Pointer Register (offset) */
|
|
#define INTELXL_QXX_TAIL 0x8000
|
|
|
|
/** Global RLAN Control 0 register */
|
|
#define INTELXL_GLLAN_RCTL_0 0x12a500
|
|
#define INTELXL_GLLAN_RCTL_0_PXE_MODE 0x00000001UL /**< PXE mode */
|
|
|
|
/** Transmit data descriptor */
|
|
struct intelxl_tx_data_descriptor {
|
|
/** Buffer address */
|
|
uint64_t address;
|
|
/** Flags */
|
|
uint32_t flags;
|
|
/** Length */
|
|
uint32_t len;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** Transmit data descriptor type */
|
|
#define INTELXL_TX_DATA_DTYP 0x0
|
|
|
|
/** Transmit data descriptor end of packet */
|
|
#define INTELXL_TX_DATA_EOP 0x10
|
|
|
|
/** Transmit data descriptor report status */
|
|
#define INTELXL_TX_DATA_RS 0x20
|
|
|
|
/** Transmit data descriptor pretty please
|
|
*
|
|
* This bit is completely missing from older versions of the XL710
|
|
* datasheet. Later versions describe it innocuously as "reserved,
|
|
* must be 1". Without this bit, everything will appear to work (up
|
|
* to and including the port "transmit good octets" counter), but no
|
|
* packet will actually be sent.
|
|
*/
|
|
#define INTELXL_TX_DATA_JFDI 0x40
|
|
|
|
/** Transmit data descriptor length */
|
|
#define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 )
|
|
|
|
/** Transmit writeback descriptor */
|
|
struct intelxl_tx_writeback_descriptor {
|
|
/** Reserved */
|
|
uint8_t reserved_a[8];
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Reserved */
|
|
uint8_t reserved_b[7];
|
|
} __attribute__ (( packed ));
|
|
|
|
/** Transmit writeback descriptor complete */
|
|
#define INTELXL_TX_WB_FL_DD 0x01
|
|
|
|
/** Transmit descriptor */
|
|
union intelxl_tx_descriptor {
|
|
/** Transmit data descriptor */
|
|
struct intelxl_tx_data_descriptor data;
|
|
/** Transmit writeback descriptor */
|
|
struct intelxl_tx_writeback_descriptor wb;
|
|
};
|
|
|
|
/** Receive data descriptor */
|
|
struct intelxl_rx_data_descriptor {
|
|
/** Buffer address */
|
|
uint64_t address;
|
|
/** Flags */
|
|
uint32_t flags;
|
|
/** Reserved */
|
|
uint8_t reserved[20];
|
|
} __attribute__ (( packed ));
|
|
|
|
/** Receive writeback descriptor */
|
|
struct intelxl_rx_writeback_descriptor {
|
|
/** Reserved */
|
|
uint8_t reserved_a[2];
|
|
/** VLAN tag */
|
|
uint16_t vlan;
|
|
/** Reserved */
|
|
uint8_t reserved_b[4];
|
|
/** Flags */
|
|
uint32_t flags;
|
|
/** Length */
|
|
uint32_t len;
|
|
/** Reserved */
|
|
uint8_t reserved_c[16];
|
|
} __attribute__ (( packed ));
|
|
|
|
/** Receive writeback descriptor complete */
|
|
#define INTELXL_RX_WB_FL_DD 0x00000001UL
|
|
|
|
/** Receive writeback descriptor VLAN tag present */
|
|
#define INTELXL_RX_WB_FL_VLAN 0x00000004UL
|
|
|
|
/** Receive writeback descriptor error */
|
|
#define INTELXL_RX_WB_FL_RXE 0x00080000UL
|
|
|
|
/** Receive writeback descriptor length */
|
|
#define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
|
|
|
|
/** Packet descriptor */
|
|
union intelxl_rx_descriptor {
|
|
/** Receive data descriptor */
|
|
struct intelxl_rx_data_descriptor data;
|
|
/** Receive writeback descriptor */
|
|
struct intelxl_rx_writeback_descriptor wb;
|
|
};
|
|
|
|
/** Descriptor ring */
|
|
struct intelxl_ring {
|
|
/** Descriptors */
|
|
union {
|
|
/** Transmit descriptors */
|
|
union intelxl_tx_descriptor *tx;
|
|
/** Receive descriptors */
|
|
union intelxl_rx_descriptor *rx;
|
|
/** Raw data */
|
|
void *raw;
|
|
} desc;
|
|
/** Descriptor ring DMA mapping */
|
|
struct dma_mapping map;
|
|
/** Producer index */
|
|
unsigned int prod;
|
|
/** Consumer index */
|
|
unsigned int cons;
|
|
|
|
/** Register block */
|
|
unsigned int reg;
|
|
/** Tail register */
|
|
unsigned int tail;
|
|
/** Length (in bytes) */
|
|
size_t len;
|
|
/** Program queue context
|
|
*
|
|
* @v intelxl Intel device
|
|
* @v address Descriptor ring base address
|
|
*/
|
|
int ( * context ) ( struct intelxl_nic *intelxl, physaddr_t address );
|
|
};
|
|
|
|
/**
|
|
* Initialise descriptor ring
|
|
*
|
|
* @v ring Descriptor ring
|
|
* @v count Number of descriptors
|
|
* @v len Length of a single descriptor
|
|
* @v context Method to program queue context
|
|
*/
|
|
static inline __attribute__ (( always_inline)) void
|
|
intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count, size_t len,
|
|
int ( * context ) ( struct intelxl_nic *intelxl,
|
|
physaddr_t address ) ) {
|
|
|
|
ring->len = ( count * len );
|
|
ring->context = context;
|
|
}
|
|
|
|
/** Number of transmit descriptors
|
|
*
|
|
* Chosen to exceed the receive ring fill level, in order to avoid
|
|
* running out of transmit descriptors when sending TCP ACKs.
|
|
*/
|
|
#define INTELXL_TX_NUM_DESC 64
|
|
|
|
/** Transmit descriptor ring maximum fill level */
|
|
#define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
|
|
|
|
/** Number of receive descriptors
|
|
*
|
|
* Must be a multiple of 32.
|
|
*/
|
|
#define INTELXL_RX_NUM_DESC 32
|
|
|
|
/** Receive descriptor ring fill level
|
|
*
|
|
* Must be a multiple of 8 and greater than 8.
|
|
*/
|
|
#define INTELXL_RX_FILL 16
|
|
|
|
/******************************************************************************
|
|
*
|
|
* Top level
|
|
*
|
|
******************************************************************************
|
|
*/
|
|
|
|
/** PF Interrupt Zero Dynamic Control Register */
|
|
#define INTELXL_PFINT_DYN_CTL0 0x038480
|
|
#define INTELXL_INT_DYN_CTL_INTENA 0x00000001UL /**< Enable */
|
|
#define INTELXL_INT_DYN_CTL_CLEARPBA 0x00000002UL /**< Acknowledge */
|
|
#define INTELXL_INT_DYN_CTL_INTENA_MASK 0x80000000UL /**< Ignore enable */
|
|
|
|
/** PF Interrupt Zero Linked List Register */
|
|
#define INTELXL_PFINT_LNKLST0 0x038500
|
|
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \
|
|
( (x) << 0 ) /**< Queue index */
|
|
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \
|
|
INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) /**< End of list */
|
|
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \
|
|
( (x) << 11 ) /**< Queue type */
|
|
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \
|
|
INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) /**< Receive queue */
|
|
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \
|
|
INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) /**< Transmit queue */
|
|
|
|
/** PF Interrupt Zero Cause Enablement Register */
|
|
#define INTELXL_PFINT_ICR0_ENA 0x038800
|
|
#define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL /**< Admin event */
|
|
|
|
/** Receive Queue Interrupt Cause Control Register */
|
|
#define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
|
|
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
|
|
#define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \
|
|
INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
|
|
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
|
|
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \
|
|
INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
|
|
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \
|
|
INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
|
|
#define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
|
|
|
|
/** Transmit Queue Interrupt Cause Control Register */
|
|
#define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
|
|
#define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
|
|
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \
|
|
INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
|
|
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
|
|
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \
|
|
INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
|
|
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \
|
|
INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
|
|
#define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
|
|
|
|
/** PF Control Register */
|
|
#define INTELXL_PFGEN_CTRL 0x092400
|
|
#define INTELXL_PFGEN_CTRL_PFSWR 0x00000001UL /**< Software Reset */
|
|
|
|
/** Time to delay for device reset, in milliseconds */
|
|
#define INTELXL_RESET_DELAY_MS 100
|
|
|
|
/** Function Requester ID Information Register */
|
|
#define INTELXL_PFFUNC_RID 0x09c000
|
|
#define INTELXL_PFFUNC_RID_FUNC_NUM(x) \
|
|
( ( (x) >> 0 ) & 0x7 ) /**< Function number */
|
|
|
|
/** PF Queue Allocation Register */
|
|
#define INTELXL_PFLAN_QALLOC 0x1c0400
|
|
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \
|
|
( ( (x) >> 0 ) & 0x7ff ) /**< First queue */
|
|
#define INTELXL_PFLAN_QALLOC_LASTQ(x) \
|
|
( ( (x) >> 16 ) & 0x7ff ) /**< Last queue */
|
|
|
|
/** PF LAN Port Number Register */
|
|
#define INTELXL_PFGEN_PORTNUM 0x1c0480
|
|
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \
|
|
( ( (x) >> 0 ) & 0x3 ) /**< Port number */
|
|
|
|
/** Port MAC Address Low Register */
|
|
#define INTELXL_PRTGL_SAL 0x1e2120
|
|
|
|
/** Port MAC Address High Register */
|
|
#define INTELXL_PRTGL_SAH 0x1e2140
|
|
#define INTELXL_PRTGL_SAH_MFS_GET(x) ( (x) >> 16 ) /**< Max frame size */
|
|
#define INTELXL_PRTGL_SAH_MFS_SET(x) ( (x) << 16 ) /**< Max frame size */
|
|
|
|
/** Physical Function MAC Address Low Register */
|
|
#define INTELXL_PRTPM_SAL 0x1e4440
|
|
|
|
/** Physical Function MAC Address High Register */
|
|
#define INTELXL_PRTPM_SAH 0x1e44c0
|
|
|
|
/** Receive address */
|
|
union intelxl_receive_address {
|
|
struct {
|
|
uint32_t low;
|
|
uint32_t high;
|
|
} __attribute__ (( packed )) reg;
|
|
uint8_t raw[ETH_ALEN];
|
|
};
|
|
|
|
/** MSI-X interrupt */
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struct intelxl_msix {
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/** PCI capability */
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struct pci_msix cap;
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/** MSI-X dummy interrupt target */
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uint32_t msg;
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/** DMA mapping for dummy interrupt target */
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struct dma_mapping map;
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};
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/** An Intel 40Gigabit network card */
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struct intelxl_nic {
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/** Registers */
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void *regs;
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/** DMA device */
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struct dma_device *dma;
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/** Maximum frame size */
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size_t mfs;
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/** Physical function number */
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unsigned int pf;
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/** Absolute queue number base */
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unsigned int base;
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/** Port number */
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unsigned int port;
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/** Queue number */
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unsigned int queue;
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/** Virtual Station Interface switching element ID */
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unsigned int vsi;
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/** Queue set handle */
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|
unsigned int qset;
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/** Interrupt control register */
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unsigned int intr;
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/** PCI Express capability offset */
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unsigned int exp;
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/** MSI-X interrupt */
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struct intelxl_msix msix;
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/** Admin command queue */
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struct intelxl_admin command;
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/** Admin event queue */
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struct intelxl_admin event;
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/** Current VF opcode */
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unsigned int vopcode;
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/** Current VF return value */
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int vret;
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/** Current VF event data buffer */
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union intelxl_admin_buffer vbuf;
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|
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/** Transmit descriptor ring */
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struct intelxl_ring tx;
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/** Receive descriptor ring */
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struct intelxl_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[INTELXL_RX_NUM_DESC];
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};
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extern int intelxl_msix_enable ( struct intelxl_nic *intelxl,
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struct pci_device *pci );
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extern void intelxl_msix_disable ( struct intelxl_nic *intelxl,
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|
struct pci_device *pci );
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|
extern struct intelxl_admin_descriptor *
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|
intelxl_admin_command_descriptor ( struct intelxl_nic *intelxl );
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extern union intelxl_admin_buffer *
|
|
intelxl_admin_command_buffer ( struct intelxl_nic *intelxl );
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extern int intelxl_admin_command ( struct intelxl_nic *intelxl );
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extern void intelxl_poll_admin ( struct net_device *netdev );
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extern int intelxl_open_admin ( struct intelxl_nic *intelxl );
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extern void intelxl_reopen_admin ( struct intelxl_nic *intelxl );
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extern void intelxl_close_admin ( struct intelxl_nic *intelxl );
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extern int intelxl_alloc_ring ( struct intelxl_nic *intelxl,
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|
struct intelxl_ring *ring );
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extern void intelxl_free_ring ( struct intelxl_nic *intelxl,
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|
struct intelxl_ring *ring );
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|
extern void intelxl_empty_rx ( struct intelxl_nic *intelxl );
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extern int intelxl_transmit ( struct net_device *netdev,
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|
struct io_buffer *iobuf );
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extern void intelxl_poll ( struct net_device *netdev );
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|
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extern void intelxlvf_admin_event ( struct net_device *netdev,
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struct intelxl_admin_descriptor *evt,
|
|
union intelxl_admin_buffer *buf );
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|
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#endif /* _INTELXL_H */
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