mirror of https://github.com/ipxe/ipxe.git
207 lines
5.3 KiB
C
207 lines
5.3 KiB
C
#ifndef _ICPLUS_H
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#define _ICPLUS_H
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/** @file
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*
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* IC+ network driver
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*
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*/
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#include <ipxe/nvs.h>
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#include <ipxe/mii_bit.h>
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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/** BAR size */
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#define ICP_BAR_SIZE 0x200
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/** Alignment requirement */
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#define ICP_ALIGN 0x8
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/** Base address low register offset */
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#define ICP_BASE_LO 0x0
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/** Base address high register offset */
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#define ICP_BASE_HI 0x4
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/** ASIC control register (double word) */
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#define ICP_ASICCTRL 0x30
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#define ICP_ASICCTRL_PHYSPEED1000 0x00000040UL /**< PHY speed 1000 */
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#define ICP_ASICCTRL_GLOBALRESET 0x00010000UL /**< Global reset */
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#define ICP_ASICCTRL_DMA 0x00080000UL /**< DMA */
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#define ICP_ASICCTRL_FIFO 0x00100000UL /**< FIFO */
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#define ICP_ASICCTRL_NETWORK 0x00200000UL /**< Network */
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#define ICP_ASICCTRL_HOST 0x00400000UL /**< Host */
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#define ICP_ASICCTRL_AUTOINIT 0x00800000UL /**< Auto init */
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#define ICP_ASICCTRL_RESETBUSY 0x04000000UL /**< Reset busy */
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/** Maximum time to wait for reset */
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#define ICP_RESET_MAX_WAIT_MS 1000
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/** DMA control register (word/double word) */
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#define ICP_DMACTRL 0x00
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#define ICP_DMACTRL_RXPOLLNOW 0x0010 /**< Receive poll now */
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#define ICP_DMACTRL_TXPOLLNOW 0x1000 /**< Transmit poll now */
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/** EEPROM control register (word) */
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#define ICP_EEPROMCTRL 0x4a
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#define ICP_EEPROMCTRL_ADDRESS( x ) ( (x) << 0 ) /**< Address */
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#define ICP_EEPROMCTRL_OPCODE( x ) ( (x) << 8 ) /**< Opcode */
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#define ICP_EEPROMCTRL_OPCODE_READ \
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ICP_EEPROMCTRL_OPCODE ( 2 ) /**< Read register */
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#define ICP_EEPROMCTRL_BUSY 0x8000 /**< EEPROM busy */
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/** Maximum time to wait for reading EEPROM */
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#define ICP_EEPROM_MAX_WAIT_MS 1000
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/** EEPROM word length */
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#define ICP_EEPROM_WORD_LEN_LOG2 1
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/** Minimum EEPROM size, in words */
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#define ICP_EEPROM_MIN_SIZE_WORDS 0x20
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/** Address of MAC address within EEPROM */
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#define ICP_EEPROM_MAC 0x10
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/** EEPROM data register (word) */
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#define ICP_EEPROMDATA 0x48
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/** Interupt status register (word) */
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#define ICP_INTSTATUS 0x5e
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#define ICP_INTSTATUS_TXCOMPLETE 0x0004 /**< TX complete */
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#define ICP_INTSTATUS_LINKEVENT 0x0100 /**< Link event */
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#define ICP_INTSTATUS_RXDMACOMPLETE 0x0400 /**< RX DMA complete */
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/** MAC control register (double word) */
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#define ICP_MACCTRL 0x6c
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#define ICP_MACCTRL_DUPLEX 0x00000020UL /**< Duplex select */
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#define ICP_MACCTRL_TXENABLE 0x01000000UL /**< TX enable */
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#define ICP_MACCTRL_TXDISABLE 0x02000000UL /**< TX disable */
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#define ICP_MACCTRL_RXENABLE 0x08000000UL /**< RX enable */
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#define ICP_MACCTRL_RXDISABLE 0x10000000UL /**< RX disable */
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/** PHY control register (byte) */
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#define ICP_PHYCTRL 0x76
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#define ICP_PHYCTRL_MGMTCLK 0x01 /**< Management clock */
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#define ICP_PHYCTRL_MGMTDATA 0x02 /**< Management data */
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#define ICP_PHYCTRL_MGMTDIR 0x04 /**< Management direction */
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#define ICP_PHYCTRL_LINKSPEED 0xc0 /**< Link speed */
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/** Receive mode register (word) */
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#define ICP_RXMODE 0x88
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#define ICP_RXMODE_UNICAST 0x0001 /**< Receive unicast */
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#define ICP_RXMODE_MULTICAST 0x0002 /**< Receice multicast */
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#define ICP_RXMODE_BROADCAST 0x0004 /**< Receive broadcast */
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#define ICP_RXMODE_ALLFRAMES 0x0008 /**< Receive all frames */
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/** List pointer receive register */
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#define ICP_RFDLISTPTR 0x1c
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/** List pointer transmit register */
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#define ICP_TFDLISTPTR 0x10
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/** Transmit status register */
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#define ICP_TXSTATUS 0x60
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#define ICP_TXSTATUS_ERROR 0x00000001UL /**< TX error */
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/** Data fragment */
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union icplus_fragment {
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/** Address of data */
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uint64_t address;
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/** Length */
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struct {
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/** Reserved */
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uint8_t reserved[6];
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/** Length of data */
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uint16_t len;
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};
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};
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/** Transmit or receive descriptor */
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struct icplus_descriptor {
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/** Address of next descriptor */
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uint64_t next;
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/** Actual length */
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uint16_t len;
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/** Flags */
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uint8_t flags;
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/** Control */
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uint8_t control;
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/** VLAN */
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uint16_t vlan;
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/** Reserved */
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uint16_t reserved_a;
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/** Data buffer */
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union icplus_fragment data;
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/** Reserved */
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uint8_t reserved_b[8];
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};
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/** Descriptor complete */
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#define ICP_DONE 0x80
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/** Transmit alignment disabled */
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#define ICP_TX_UNALIGN 0x01
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/** Request transmit completion */
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#define ICP_TX_INDICATE 0x40
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/** Sole transmit fragment */
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#define ICP_TX_SOLE_FRAG 0x01
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/** Recieve frame overrun error */
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#define ICP_RX_ERR_OVERRUN 0x01
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/** Receive runt frame error */
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#define ICP_RX_ERR_RUNT 0x02
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/** Receive alignment error */
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#define ICP_RX_ERR_ALIGN 0x04
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/** Receive FCS error */
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#define ICP_RX_ERR_FCS 0x08
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/** Receive oversized frame error */
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#define ICP_RX_ERR_OVERSIZED 0x10
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/** Recieve length error */
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#define ICP_RX_ERR_LEN 0x20
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/** Descriptor ring */
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struct icplus_ring {
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/** Producer counter */
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unsigned int prod;
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/** Consumer counter */
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unsigned int cons;
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/** Ring entries */
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struct icplus_descriptor *entry;
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/* List pointer register */
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unsigned int listptr;
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};
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/** Number of descriptors */
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#define ICP_NUM_DESC 4
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/** Maximum receive packet length */
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#define ICP_RX_MAX_LEN ETH_FRAME_LEN
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/** An IC+ network card */
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struct icplus_nic {
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/** Registers */
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void *regs;
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/** EEPROM */
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struct nvs_device eeprom;
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/** MII bit bashing interface */
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struct mii_bit_basher miibit;
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/** MII device */
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struct mii_device mii;
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/** Transmit descriptor ring */
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struct icplus_ring tx;
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/** Receive descriptor ring */
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struct icplus_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[ICP_NUM_DESC];
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};
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#endif /* _ICPLUS_H */
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