mirror of https://github.com/ipxe/ipxe.git
[intelxl] Add driver for Intel 40 Gigabit Ethernet NICs
Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/76/head
Michael Brown
parent
b9d68b9de0
commit
d2063b7693
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#ifndef _INTELX_H
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#define _INTELX_H
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/** @file
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*
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* Intel 40 Gigabit Ethernet network card driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/if_ether.h>
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struct intelxl_nic;
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/** BAR size */
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#define INTELXL_BAR_SIZE 0x200000
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/** Alignment
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*
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* No data structure requires greater than 128 byte alignment.
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*/
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#define INTELXL_ALIGN 128
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/******************************************************************************
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*
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* Admin queue
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*
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******************************************************************************
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*/
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/** PF Admin Command Queue register block */
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#define INTELXL_ADMIN_CMD 0x080000
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/** PF Admin Event Queue register block */
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#define INTELXL_ADMIN_EVT 0x080080
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/** Admin Queue Base Address Low Register (offset) */
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#define INTELXL_ADMIN_BAL 0x000
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/** Admin Queue Base Address High Register (offset) */
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#define INTELXL_ADMIN_BAH 0x100
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/** Admin Queue Length Register (offset) */
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#define INTELXL_ADMIN_LEN 0x200
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#define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) /**< Queue length */
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#define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL /**< Queue enable */
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/** Admin Queue Head Register (offset) */
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#define INTELXL_ADMIN_HEAD 0x300
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/** Admin Queue Tail Register (offset) */
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#define INTELXL_ADMIN_TAIL 0x400
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/** Admin queue data buffer command parameters */
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struct intelxl_admin_buffer_params {
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/** Reserved */
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uint8_t reserved[8];
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/** Buffer address high */
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uint32_t high;
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/** Buffer address low */
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uint32_t low;
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} __attribute__ (( packed ));
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/** Admin queue Get Version command */
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#define INTELXL_ADMIN_VERSION 0x0001
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/** Admin queue version number */
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struct intelxl_admin_version {
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/** Major version number */
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uint16_t major;
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/** Minor version number */
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uint16_t minor;
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} __attribute__ (( packed ));
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/** Admin queue Get Version command parameters */
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struct intelxl_admin_version_params {
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/** ROM version */
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uint32_t rom;
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/** Firmware build ID */
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uint32_t build;
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/** Firmware version */
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struct intelxl_admin_version firmware;
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/** API version */
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struct intelxl_admin_version api;
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} __attribute__ (( packed ));
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/** Admin queue Driver Version command */
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#define INTELXL_ADMIN_DRIVER 0x0002
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/** Admin queue Driver Version command parameters */
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struct intelxl_admin_driver_params {
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/** Driver version */
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uint8_t major;
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/** Minor version */
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uint8_t minor;
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/** Build version */
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uint8_t build;
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/** Sub-build version */
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uint8_t sub;
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/** Reserved */
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uint8_t reserved[4];
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/** Data buffer address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Admin queue Driver Version data buffer */
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struct intelxl_admin_driver_buffer {
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/** Driver name */
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char name[32];
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} __attribute__ (( packed ));
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/** Admin queue Shutdown command */
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#define INTELXL_ADMIN_SHUTDOWN 0x0003
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/** Admin queue Shutdown command parameters */
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struct intelxl_admin_shutdown_params {
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/** Driver unloading */
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uint8_t unloading;
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/** Reserved */
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uint8_t reserved[15];
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} __attribute__ (( packed ));
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/** Driver is unloading */
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#define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
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/** Admin queue Get Switch Configuration command */
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#define INTELXL_ADMIN_SWITCH 0x0200
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/** Switching element configuration */
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struct intelxl_admin_switch_config {
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/** Switching element type */
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uint8_t type;
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/** Revision */
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uint8_t revision;
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/** Switching element ID */
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uint16_t seid;
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/** Uplink switching element ID */
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uint16_t uplink;
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/** Downlink switching element ID */
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uint16_t downlink;
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/** Reserved */
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uint8_t reserved_b[3];
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/** Connection type */
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uint8_t connection;
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/** Reserved */
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uint8_t reserved_c[2];
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/** Element specific information */
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uint16_t info;
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} __attribute__ (( packed ));
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/** Virtual Station Inferface element type */
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#define INTELXL_ADMIN_SWITCH_TYPE_VSI 19
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/** Admin queue Get Switch Configuration command parameters */
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struct intelxl_admin_switch_params {
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/** Starting switching element identifier */
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uint16_t next;
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/** Reserved */
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uint8_t reserved[6];
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/** Data buffer address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Admin queue Get Switch Configuration data buffer */
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struct intelxl_admin_switch_buffer {
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/** Number of switching elements reported */
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uint16_t count;
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/** Total number of switching elements */
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uint16_t total;
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/** Reserved */
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uint8_t reserved_a[12];
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/** Switch configuration */
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struct intelxl_admin_switch_config cfg;
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} __attribute__ (( packed ));
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/** Admin queue Get VSI Parameters command */
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#define INTELXL_ADMIN_VSI 0x0212
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/** Admin queue Get VSI Parameters command parameters */
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struct intelxl_admin_vsi_params {
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/** VSI switching element ID */
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uint16_t vsi;
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/** Reserved */
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uint8_t reserved[6];
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/** Data buffer address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Admin queue Get VSI Parameters data buffer */
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struct intelxl_admin_vsi_buffer {
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/** Reserved */
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uint8_t reserved_a[30];
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/** Queue numbers */
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uint16_t queue[16];
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/** Reserved */
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uint8_t reserved_b[34];
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/** Queue set handles for each traffic class */
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uint16_t qset[8];
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/** Reserved */
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uint8_t reserved_c[16];
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} __attribute__ (( packed ));
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/** Admin queue Set VSI Promiscuous Modes command */
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#define INTELXL_ADMIN_PROMISC 0x0254
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/** Admin queue Set VSI Promiscuous Modes command parameters */
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struct intelxl_admin_promisc_params {
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/** Flags */
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uint16_t flags;
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/** Valid flags */
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uint16_t valid;
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/** VSI switching element ID */
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uint16_t vsi;
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/** Reserved */
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uint8_t reserved[10];
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} __attribute__ (( packed ));
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/** Promiscuous unicast mode */
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#define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
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/** Promiscuous multicast mode */
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#define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
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/** Promiscuous broadcast mode */
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#define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
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/** Promiscuous VLAN mode */
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#define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
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/** Admin queue Restart Autonegotiation command */
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#define INTELXL_ADMIN_AUTONEG 0x0605
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/** Admin queue Restart Autonegotiation command parameters */
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struct intelxl_admin_autoneg_params {
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/** Flags */
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uint8_t flags;
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/** Reserved */
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uint8_t reserved[15];
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} __attribute__ (( packed ));
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/** Restart autonegotiation */
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#define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
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/** Enable link */
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#define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
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/** Admin queue Get Link Status command */
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#define INTELXL_ADMIN_LINK 0x0607
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/** Admin queue Get Link Status command parameters */
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struct intelxl_admin_link_params {
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/** Link status notification */
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uint8_t notify;
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/** Reserved */
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uint8_t reserved_a;
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/** PHY type */
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uint8_t phy;
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/** Link speed */
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uint8_t speed;
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/** Link status */
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uint8_t status;
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/** Reserved */
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uint8_t reserved_b[11];
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} __attribute__ (( packed ));
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/** Notify driver of link status changes */
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#define INTELXL_ADMIN_LINK_NOTIFY 0x03
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/** Link is up */
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#define INTELXL_ADMIN_LINK_UP 0x01
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/** Admin queue command parameters */
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union intelxl_admin_params {
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/** Additional data buffer command parameters */
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struct intelxl_admin_buffer_params buffer;
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/** Get Version command parameters */
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struct intelxl_admin_version_params version;
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/** Driver Version command parameters */
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struct intelxl_admin_driver_params driver;
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/** Shutdown command parameters */
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struct intelxl_admin_shutdown_params shutdown;
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/** Get Switch Configuration command parameters */
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struct intelxl_admin_switch_params sw;
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/** Get VSI Parameters command parameters */
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struct intelxl_admin_vsi_params vsi;
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/** Set VSI Promiscuous Modes command parameters */
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struct intelxl_admin_promisc_params promisc;
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/** Restart Autonegotiation command parameters */
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struct intelxl_admin_autoneg_params autoneg;
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/** Get Link Status command parameters */
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struct intelxl_admin_link_params link;
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} __attribute__ (( packed ));
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/** Admin queue data buffer */
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union intelxl_admin_buffer {
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/** Driver Version data buffer */
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struct intelxl_admin_driver_buffer driver;
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/** Get Switch Configuration data buffer */
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struct intelxl_admin_switch_buffer sw;
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/** Get VSI Parameters data buffer */
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struct intelxl_admin_vsi_buffer vsi;
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} __attribute__ (( packed ));
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/** Admin queue descriptor */
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struct intelxl_admin_descriptor {
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/** Flags */
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uint16_t flags;
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/** Opcode */
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uint16_t opcode;
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/** Data length */
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uint16_t len;
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/** Return value */
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uint16_t ret;
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/** Cookie */
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uint32_t cookie;
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/** Reserved */
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uint32_t reserved;
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/** Parameters */
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union intelxl_admin_params params;
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} __attribute__ (( packed ));
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/** Admin descriptor done */
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#define INTELXL_ADMIN_FL_DD 0x0001
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/** Admin descriptor contains a completion */
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#define INTELXL_ADMIN_FL_CMP 0x0002
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/** Admin descriptor completed in error */
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#define INTELXL_ADMIN_FL_ERR 0x0004
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/** Admin descriptor uses data buffer for command parameters */
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#define INTELXL_ADMIN_FL_RD 0x0400
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/** Admin descriptor uses data buffer */
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#define INTELXL_ADMIN_FL_BUF 0x1000
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/** Admin queue */
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struct intelxl_admin {
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/** Descriptors */
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struct intelxl_admin_descriptor *desc;
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/** Queue index */
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unsigned int index;
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/** Register block */
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unsigned int reg;
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/** Data buffer */
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union intelxl_admin_buffer *buffer;
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};
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/**
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* Initialise admin queue
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*
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* @v admin Admin queue
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* @v reg Register block
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*/
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static inline __attribute__ (( always_inline )) void
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intelxl_init_admin ( struct intelxl_admin *admin, unsigned int reg ) {
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admin->reg = reg;
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}
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/** Number of admin queue descriptors */
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#define INTELXL_ADMIN_NUM_DESC 4
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/** Maximum time to wait for an admin request to complete */
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#define INTELXL_ADMIN_MAX_WAIT_MS 100
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/** Admin queue API major version */
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#define INTELXL_ADMIN_API_MAJOR 1
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/******************************************************************************
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*
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* Transmit and receive queue context
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*
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******************************************************************************
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*/
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/** CMLAN Context Data Register */
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#define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
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/** CMLAN Context Control Register */
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#define INTELXL_PFCM_LANCTXCTL 0x10c300
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#define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \
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( (x) << 0 ) /**< Queue number */
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#define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \
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( (x) << 12 ) /**< Sub-line */
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#define INTELXL_PFCM_LANCTXCTL_TYPE(x) \
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( (x) << 15 ) /**< Queue type */
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#define INTELXL_PFCM_LANCTXCTL_TYPE_RX \
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INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) /**< RX queue type */
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#define INTELXL_PFCM_LANCTXCTL_TYPE_TX \
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INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) /**< TX queue type */
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#define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \
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( (x) << 17 ) /**< Op code */
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#define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \
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INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) /**< Read context */
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#define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \
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INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) /**< Write context */
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/** CMLAN Context Status Register */
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#define INTELXL_PFCM_LANCTXSTAT 0x10c380
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#define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL /**< Complete */
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/** Queue context line */
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struct intelxl_context_line {
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/** Raw data */
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uint32_t raw[4];
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} __attribute__ (( packed ));
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/** Transmit queue context */
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struct intelxl_context_tx {
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/** Head pointer */
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uint16_t head;
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/** Flags */
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uint16_t flags;
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/** Base address */
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uint64_t base;
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/** Reserved */
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uint8_t reserved_a[8];
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/** Queue count */
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uint16_t count;
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/** Reserved */
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uint8_t reserved_b[100];
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/** Queue set */
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uint16_t qset;
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/** Reserved */
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uint8_t reserved_c[4];
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} __attribute__ (( packed ));
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/** New transmit queue context */
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#define INTELXL_CTX_TX_FL_NEW 0x4000
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/** Transmit queue base address */
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#define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 )
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/** Transmit queue count */
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#define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 )
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/** Transmit queue set */
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#define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 )
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/** Receive queue context */
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struct intelxl_context_rx {
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/** Head pointer */
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uint16_t head;
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/** Reserved */
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uint8_t reserved_a[2];
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/** Base address and queue count */
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uint64_t base_count;
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/** Data buffer length */
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uint16_t len;
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/** Flags */
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uint8_t flags;
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/** Reserved */
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uint8_t reserved_b[7];
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/** Maximum frame size */
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uint16_t mfs;
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} __attribute__ (( packed ));
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/** Receive queue base address and queue count */
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#define INTELXL_CTX_RX_BASE_COUNT( base, count ) \
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( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
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/** Receive queue data buffer length */
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#define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 )
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/** Strip CRC from received packets */
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#define INTELXL_CTX_RX_FL_CRCSTRIP 0x20
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/** Receive queue maximum frame size */
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#define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 )
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/** Maximum time to wait for a context operation to complete */
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#define INTELXL_CTX_MAX_WAIT_MS 100
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/** Time to wait for a queue to become enabled */
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#define INTELXL_QUEUE_ENABLE_DELAY_US 20
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/** Time to wait for a transmit queue to become pre-disabled */
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#define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
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/** Maximum time to wait for a queue to become disabled */
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#define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
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/******************************************************************************
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*
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* Transmit and receive descriptors
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*
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******************************************************************************
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*/
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/** Global Transmit Queue Head register */
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#define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
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/** Global Transmit Pre Queue Disable register */
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#define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
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#define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \
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( (x) << 0 ) /**< Queue index */
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#define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \
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0x40000000UL /**< Set disable */
|
||||
#define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \
|
||||
0x80000000UL /**< Clear disable */
|
||||
|
||||
/** Global Transmit Queue register block */
|
||||
#define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
|
||||
|
||||
/** Global Receive Queue register block */
|
||||
#define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
|
||||
|
||||
/** Queue Enable Register (offset) */
|
||||
#define INTELXL_QXX_ENA 0x0000
|
||||
#define INTELXL_QXX_ENA_REQ 0x00000001UL /**< Enable request */
|
||||
#define INTELXL_QXX_ENA_STAT 0x00000004UL /**< Enabled status */
|
||||
|
||||
/** Queue Control Register (offset) */
|
||||
#define INTELXL_QXX_CTL 0x4000
|
||||
#define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) /**< PF/VF queue */
|
||||
#define INTELXL_QXX_CTL_PFVF_Q_PF \
|
||||
INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) /**< PF queue */
|
||||
#define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) /**< PF index */
|
||||
|
||||
/** Queue Tail Pointer Register (offset) */
|
||||
#define INTELXL_QXX_TAIL 0x8000
|
||||
|
||||
/** Transmit data descriptor */
|
||||
struct intelxl_tx_data_descriptor {
|
||||
/** Buffer address */
|
||||
uint64_t address;
|
||||
/** Flags */
|
||||
uint32_t flags;
|
||||
/** Length */
|
||||
uint32_t len;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** Transmit data descriptor type */
|
||||
#define INTELXL_TX_DATA_DTYP 0x0
|
||||
|
||||
/** Transmit data descriptor end of packet */
|
||||
#define INTELXL_TX_DATA_EOP 0x10
|
||||
|
||||
/** Transmit data descriptor report status */
|
||||
#define INTELXL_TX_DATA_RS 0x20
|
||||
|
||||
/** Transmit data descriptor pretty please
|
||||
*
|
||||
* This bit is completely missing from older versions of the XL710
|
||||
* datasheet. Later versions describe it innocuously as "reserved,
|
||||
* must be 1". Without this bit, everything will appear to work (up
|
||||
* to and including the port "transmit good octets" counter), but no
|
||||
* packet will actually be sent.
|
||||
*/
|
||||
#define INTELXL_TX_DATA_JFDI 0x40
|
||||
|
||||
/** Transmit data descriptor length */
|
||||
#define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 )
|
||||
|
||||
/** Transmit writeback descriptor */
|
||||
struct intelxl_tx_writeback_descriptor {
|
||||
/** Reserved */
|
||||
uint8_t reserved_a[8];
|
||||
/** Flags */
|
||||
uint8_t flags;
|
||||
/** Reserved */
|
||||
uint8_t reserved_b[7];
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** Transmit writeback descriptor complete */
|
||||
#define INTELXL_TX_WB_FL_DD 0x01
|
||||
|
||||
/** Receive data descriptor */
|
||||
struct intelxl_rx_data_descriptor {
|
||||
/** Buffer address */
|
||||
uint64_t address;
|
||||
/** Flags */
|
||||
uint32_t flags;
|
||||
/** Reserved */
|
||||
uint8_t reserved[4];
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** Receive writeback descriptor */
|
||||
struct intelxl_rx_writeback_descriptor {
|
||||
/** Reserved */
|
||||
uint8_t reserved[8];
|
||||
/** Flags */
|
||||
uint32_t flags;
|
||||
/** Length */
|
||||
uint32_t len;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** Receive writeback descriptor complete */
|
||||
#define INTELXL_RX_WB_FL_DD 0x00000001UL
|
||||
|
||||
/** Receive writeback descriptor error */
|
||||
#define INTELXL_RX_WB_FL_RXE 0x00080000UL
|
||||
|
||||
/** Receive writeback descriptor length */
|
||||
#define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
|
||||
|
||||
/** Packet descriptor */
|
||||
union intelxl_descriptor {
|
||||
/** Transmit data descriptor */
|
||||
struct intelxl_tx_data_descriptor tx;
|
||||
/** Transmit writeback descriptor */
|
||||
struct intelxl_tx_writeback_descriptor tx_wb;
|
||||
/** Receive data descriptor */
|
||||
struct intelxl_rx_data_descriptor rx;
|
||||
/** Receive writeback descriptor */
|
||||
struct intelxl_rx_writeback_descriptor rx_wb;
|
||||
};
|
||||
|
||||
/** Descriptor ring */
|
||||
struct intelxl_ring {
|
||||
/** Descriptors */
|
||||
union intelxl_descriptor *desc;
|
||||
/** Producer index */
|
||||
unsigned int prod;
|
||||
/** Consumer index */
|
||||
unsigned int cons;
|
||||
|
||||
/** Register block */
|
||||
unsigned int reg;
|
||||
/** Length (in bytes) */
|
||||
size_t len;
|
||||
/** Program queue context
|
||||
*
|
||||
* @v intelxl Intel device
|
||||
* @v address Descriptor ring base address
|
||||
*/
|
||||
int ( * context ) ( struct intelxl_nic *intelxl, physaddr_t address );
|
||||
};
|
||||
|
||||
/**
|
||||
* Initialise descriptor ring
|
||||
*
|
||||
* @v ring Descriptor ring
|
||||
* @v count Number of descriptors
|
||||
* @v context Method to program queue context
|
||||
*/
|
||||
static inline __attribute__ (( always_inline)) void
|
||||
intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count,
|
||||
int ( * context ) ( struct intelxl_nic *intelxl,
|
||||
physaddr_t address ) ) {
|
||||
|
||||
ring->len = ( count * sizeof ( ring->desc[0] ) );
|
||||
ring->context = context;
|
||||
}
|
||||
|
||||
/** Number of transmit descriptors */
|
||||
#define INTELXL_TX_NUM_DESC 16
|
||||
|
||||
/** Transmit descriptor ring maximum fill level */
|
||||
#define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
|
||||
|
||||
/** Number of receive descriptors
|
||||
*
|
||||
* In PXE mode (i.e. able to post single receive descriptors), 8
|
||||
* descriptors is the only permitted value covering all possible
|
||||
* numbers of PFs.
|
||||
*/
|
||||
#define INTELXL_RX_NUM_DESC 8
|
||||
|
||||
/** Receive descriptor ring fill level */
|
||||
#define INTELXL_RX_FILL ( INTELXL_RX_NUM_DESC - 1 )
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Top level
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** PF Interrupt Zero Dynamic Control Register */
|
||||
#define INTELXL_PFINT_DYN_CTL0 0x038480
|
||||
#define INTELXL_PFINT_DYN_CTL0_INTENA 0x00000001UL /**< Enable */
|
||||
#define INTELXL_PFINT_DYN_CTL0_CLEARPBA 0x00000002UL /**< Acknowledge */
|
||||
#define INTELXL_PFINT_DYN_CTL0_INTENA_MASK 0x80000000UL /**< Ignore enable */
|
||||
|
||||
/** PF Interrupt Zero Linked List Register */
|
||||
#define INTELXL_PFINT_LNKLST0 0x038500
|
||||
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \
|
||||
( (x) << 0 ) /**< Queue index */
|
||||
#define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \
|
||||
INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) /**< End of list */
|
||||
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \
|
||||
( (x) << 11 ) /**< Queue type */
|
||||
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \
|
||||
INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) /**< Receive queue */
|
||||
#define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \
|
||||
INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) /**< Transmit queue */
|
||||
|
||||
/** PF Interrupt Zero Cause Enablement Register */
|
||||
#define INTELXL_PFINT_ICR0_ENA 0x038800
|
||||
#define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL /**< Admin event */
|
||||
|
||||
/** Receive Queue Interrupt Cause Control Register */
|
||||
#define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
|
||||
#define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
|
||||
#define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \
|
||||
INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
|
||||
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
|
||||
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \
|
||||
INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
|
||||
#define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \
|
||||
INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
|
||||
#define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
|
||||
|
||||
/** Transmit Queue Interrupt Cause Control Register */
|
||||
#define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
|
||||
#define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
|
||||
#define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \
|
||||
INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
|
||||
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
|
||||
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \
|
||||
INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
|
||||
#define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \
|
||||
INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
|
||||
#define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
|
||||
|
||||
/** PF Control Register */
|
||||
#define INTELXL_PFGEN_CTRL 0x092400
|
||||
#define INTELXL_PFGEN_CTRL_PFSWR 0x00000001UL /**< Software Reset */
|
||||
|
||||
/** Time to delay for device reset, in milliseconds */
|
||||
#define INTELXL_RESET_DELAY_MS 100
|
||||
|
||||
/** PF Queue Allocation Register */
|
||||
#define INTELXL_PFLAN_QALLOC 0x1c0400
|
||||
#define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \
|
||||
( ( (x) >> 0 ) & 0x7ff ) /**< First queue */
|
||||
#define INTELXL_PFLAN_QALLOC_LASTQ(x) \
|
||||
( ( (x) >> 16 ) & 0x7ff ) /**< Last queue */
|
||||
|
||||
/** PF LAN Port Number Register */
|
||||
#define INTELXL_PFGEN_PORTNUM 0x1c0480
|
||||
#define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \
|
||||
( ( (x) >> 0 ) & 0x3 ) /**< Port number */
|
||||
|
||||
/** Port MAC Address Low Register */
|
||||
#define INTELXL_PRTGL_SAL 0x1e2120
|
||||
|
||||
/** Port MAC Address High Register */
|
||||
#define INTELXL_PRTGL_SAH 0x1e2140
|
||||
#define INTELXL_PRTGL_SAH_MFS_GET(x) ( (x) >> 16 ) /**< Max frame size */
|
||||
#define INTELXL_PRTGL_SAH_MFS_SET(x) ( (x) << 16 ) /**< Max frame size */
|
||||
|
||||
/** Receive address */
|
||||
union intelxl_receive_address {
|
||||
struct {
|
||||
uint32_t low;
|
||||
uint32_t high;
|
||||
} __attribute__ (( packed )) reg;
|
||||
uint8_t raw[ETH_ALEN];
|
||||
};
|
||||
|
||||
/** An Intel 40Gigabit network card */
|
||||
struct intelxl_nic {
|
||||
/** Registers */
|
||||
void *regs;
|
||||
/** Maximum frame size */
|
||||
size_t mfs;
|
||||
|
||||
/** Physical function number */
|
||||
unsigned int pf;
|
||||
/** Absolute queue number base */
|
||||
unsigned int base;
|
||||
/** Port number */
|
||||
unsigned int port;
|
||||
/** Queue number */
|
||||
unsigned int queue;
|
||||
/** Virtual Station Interface switching element ID */
|
||||
unsigned int vsi;
|
||||
/** Queue set handle */
|
||||
unsigned int qset;
|
||||
|
||||
/** Admin command queue */
|
||||
struct intelxl_admin command;
|
||||
/** Admin event queue */
|
||||
struct intelxl_admin event;
|
||||
|
||||
/** Transmit descriptor ring */
|
||||
struct intelxl_ring tx;
|
||||
/** Receive descriptor ring */
|
||||
struct intelxl_ring rx;
|
||||
/** Receive I/O buffers */
|
||||
struct io_buffer *rx_iobuf[INTELXL_RX_NUM_DESC];
|
||||
};
|
||||
|
||||
#endif /* _INTELXL_H */
|
||||
|
|
@ -204,6 +204,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
|
|||
#define ERRFILE_lan78xx ( ERRFILE_DRIVER | 0x00c80000 )
|
||||
#define ERRFILE_ena ( ERRFILE_DRIVER | 0x00c90000 )
|
||||
#define ERRFILE_icplus ( ERRFILE_DRIVER | 0x00ca0000 )
|
||||
#define ERRFILE_intelxl ( ERRFILE_DRIVER | 0x00cb0000 )
|
||||
|
||||
#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
|
||||
#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )
|
||||
|
|
|
|||
Loading…
Reference in New Issue