mirror of https://github.com/ipxe/ipxe.git
[tg3] Fix compilation on newer gcc versions
Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/5/head
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f6840ba83e
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b5ed30b2d0
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@ -533,7 +533,7 @@ static int tg3_test_dma(struct tg3 *tp)
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{ DBGP("%s\n", __func__);
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dma_addr_t buf_dma;
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u32 *buf, saved_dma_rwctrl;
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u32 *buf;
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int ret = 0;
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buf = malloc_dma(TEST_BUFFER_SIZE, TG3_DMA_ALIGNMENT);
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@ -624,7 +624,6 @@ static int tg3_test_dma(struct tg3 *tp)
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/* It is best to perform DMA test with maximum write burst size
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* to expose the 5700/5701 write DMA bug.
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*/
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saved_dma_rwctrl = tp->dma_rwctrl;
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tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
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tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
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@ -1778,7 +1778,7 @@ static void tg3_rings_reset(struct tg3 *tp)
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{ DBGP("%s\n", __func__);
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int i;
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u32 stblk, txrcb, rxrcb, limit;
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u32 txrcb, rxrcb, limit;
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/* Disable all transmit rings but the first. */
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if (!tg3_flag(tp, 5705_PLUS))
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@ -1854,8 +1854,6 @@ static void tg3_rings_reset(struct tg3 *tp)
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BDINFO_FLAGS_MAXLEN_SHIFT, 0);
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rxrcb += TG3_BDINFO_SIZE;
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}
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stblk = HOSTCC_STATBLCK_RING1;
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}
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static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
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@ -2569,14 +2567,9 @@ void tg3_set_txd(struct tg3 *tp, int entry,
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u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
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{ DBGP("%s\n", __func__);
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int cacheline_size;
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u8 byte;
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pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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/* On 5703 and later chips, the boundary bits have no
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* effect.
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@ -1124,13 +1124,10 @@ static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
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static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
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{ DBGP("%s\n", __func__);
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u8 autoneg;
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u8 flowctrl = 0;
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u32 old_rx_mode = tp->rx_mode;
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u32 old_tx_mode = tp->tx_mode;
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autoneg = tp->link_config.autoneg;
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if (tg3_flag(tp, PAUSE_AUTONEG)) {
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if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
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flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
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