mirror of https://github.com/ipxe/ipxe.git
[pci] Add support for PCI MSI-X interrupts
The Intel 40 Gigabit Ethernet virtual functions support only MSI-X interrupts, and will write back completed interrupt descriptors only when the device attempts to raise an interrupt (or when a complete cacheline of receive descriptors has been completed). We cannot actually use MSI-X interrupts within iPXE, since we never have ownership of the APIC. However, an MSI-X interrupt is fundamentally just a DMA write of a single dword to an arbitrary address. We can therefore configure the device to "raise" an interrupt by writing a meaningless value to an otherwise unused memory location: this is sufficient to trigger the receive descriptor writeback logic. Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/92/head
Michael Brown
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ebf2eaf515
commit
afee77d816
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/*
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* Copyright (C) 2019 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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* You can also choose to distribute this program under the terms of
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* the Unmodified Binary Distribution Licence (as given in the file
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* COPYING.UBDL), provided that you have satisfied its requirements.
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <errno.h>
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#include <assert.h>
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#include <ipxe/pci.h>
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#include <ipxe/pcimsix.h>
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/** @file
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*
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* PCI MSI-X interrupts
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*
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*/
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/**
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* Get MSI-X descriptor name (for debugging)
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*
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* @v cfg Configuration space offset
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* @ret name Descriptor name
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*/
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static const char * pci_msix_name ( unsigned int cfg ) {
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switch ( cfg ) {
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case PCI_MSIX_DESC_TABLE: return "table";
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case PCI_MSIX_DESC_PBA: return "PBA";
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default: return "<UNKNOWN>";
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}
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}
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/**
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* Map MSI-X BAR portion
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*
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* @v pci PCI device
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* @v msix MSI-X capability
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* @v cfg Configuration space offset
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* @ret io I/O address
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*/
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static void * pci_msix_ioremap ( struct pci_device *pci, struct pci_msix *msix,
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unsigned int cfg ) {
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uint32_t desc;
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unsigned int bar;
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unsigned long start;
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unsigned long offset;
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unsigned long base;
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void *io;
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/* Read descriptor */
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pci_read_config_dword ( pci, ( msix->cap + cfg ), &desc );
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/* Get BAR */
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bar = PCI_MSIX_DESC_BIR ( desc );
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offset = PCI_MSIX_DESC_OFFSET ( desc );
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start = pci_bar_start ( pci, PCI_BASE_ADDRESS ( bar ) );
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if ( ! start ) {
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DBGC ( msix, "MSI-X %p %s could not find BAR%d\n",
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msix, pci_msix_name ( cfg ), bar );
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return NULL;
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}
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base = ( start + offset );
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DBGC ( msix, "MSI-X %p %s at %#08lx (BAR%d+%#lx)\n",
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msix, pci_msix_name ( cfg ), base, bar, offset );
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/* Map BAR portion */
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io = ioremap ( ( start + offset ), PCI_MSIX_LEN );
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if ( ! io ) {
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DBGC ( msix, "MSI-X %p %s could not map %#08lx\n",
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msix, pci_msix_name ( cfg ), base );
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return NULL;
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}
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return io;
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}
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/**
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* Enable MSI-X interrupts
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*
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* @v pci PCI device
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* @v msix MSI-X capability
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* @ret rc Return status code
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*/
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int pci_msix_enable ( struct pci_device *pci, struct pci_msix *msix ) {
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uint16_t ctrl;
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int rc;
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/* Locate capability */
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msix->cap = pci_find_capability ( pci, PCI_CAP_ID_MSIX );
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if ( ! msix->cap ) {
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DBGC ( msix, "MSI-X %p found no MSI-X capability in "
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PCI_FMT "\n", msix, PCI_ARGS ( pci ) );
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rc = -ENOENT;
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goto err_cap;
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}
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/* Extract interrupt count */
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pci_read_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), &ctrl );
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msix->count = ( PCI_MSIX_CTRL_SIZE ( ctrl ) + 1 );
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DBGC ( msix, "MSI-X %p has %d vectors for " PCI_FMT "\n",
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msix, msix->count, PCI_ARGS ( pci ) );
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/* Map MSI-X table */
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msix->table = pci_msix_ioremap ( pci, msix, PCI_MSIX_DESC_TABLE );
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if ( ! msix->table ) {
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rc = -ENOENT;
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goto err_table;
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}
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/* Map pending bit array */
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msix->pba = pci_msix_ioremap ( pci, msix, PCI_MSIX_DESC_PBA );
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if ( ! msix->pba ) {
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rc = -ENOENT;
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goto err_pba;
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}
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/* Enable MSI-X */
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ctrl &= ~PCI_MSIX_CTRL_MASK;
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ctrl |= PCI_MSIX_CTRL_ENABLE;
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pci_write_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), ctrl );
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return 0;
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iounmap ( msix->pba );
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err_pba:
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iounmap ( msix->table );
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err_table:
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err_cap:
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return rc;
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}
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/**
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* Disable MSI-X interrupts
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*
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* @v pci PCI device
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* @v msix MSI-X capability
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*/
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void pci_msix_disable ( struct pci_device *pci, struct pci_msix *msix ) {
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uint16_t ctrl;
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/* Disable MSI-X */
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pci_read_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), &ctrl );
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ctrl &= ~PCI_MSIX_CTRL_ENABLE;
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pci_write_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), ctrl );
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/* Unmap pending bit array */
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iounmap ( msix->pba );
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/* Unmap MSI-X table */
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iounmap ( msix->table );
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}
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/**
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* Map MSI-X interrupt vector
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*
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* @v msix MSI-X capability
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* @v vector MSI-X vector
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* @v address Message address
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* @v data Message data
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*/
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void pci_msix_map ( struct pci_msix *msix, unsigned int vector,
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physaddr_t address, uint32_t data ) {
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void *base;
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/* Sanity check */
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assert ( vector < msix->count );
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/* Map interrupt vector */
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base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
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writel ( ( address & 0xffffffffUL ), ( base + PCI_MSIX_ADDRESS_LO ) );
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if ( sizeof ( address ) > sizeof ( uint32_t ) ) {
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writel ( ( ( ( uint64_t ) address ) >> 32 ),
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( base + PCI_MSIX_ADDRESS_HI ) );
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} else {
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writel ( 0, ( base + PCI_MSIX_ADDRESS_HI ) );
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}
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writel ( data, ( base + PCI_MSIX_DATA ) );
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}
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/**
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* Control MSI-X interrupt vector
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*
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* @v msix MSI-X capability
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* @v vector MSI-X vector
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* @v mask Control mask
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*/
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void pci_msix_control ( struct pci_msix *msix, unsigned int vector,
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uint32_t mask ) {
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void *base;
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uint32_t ctrl;
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/* Mask/unmask interrupt vector */
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base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
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ctrl = readl ( base + PCI_MSIX_CONTROL );
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ctrl &= ~PCI_MSIX_CONTROL_MASK;
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ctrl |= mask;
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writel ( ctrl, ( base + PCI_MSIX_CONTROL ) );
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}
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/**
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* Dump MSI-X interrupt state (for debugging)
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*
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* @v msix MSI-X capability
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* @v vector MSI-X vector
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*/
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void pci_msix_dump ( struct pci_msix *msix, unsigned int vector ) {
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void *base;
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uint32_t address_hi;
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uint32_t address_lo;
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physaddr_t address;
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uint32_t data;
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uint32_t ctrl;
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uint32_t pba;
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/* Do nothing in non-debug builds */
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if ( ! DBG_LOG )
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return;
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/* Mask/unmask interrupt vector */
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base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
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address_hi = readl ( base + PCI_MSIX_ADDRESS_HI );
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address_lo = readl ( base + PCI_MSIX_ADDRESS_LO );
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data = readl ( base + PCI_MSIX_DATA );
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ctrl = readl ( base + PCI_MSIX_CONTROL );
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pba = readl ( msix->pba );
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address = ( ( ( ( uint64_t ) address_hi ) << 32 ) | address_lo );
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DBGC ( msix, "MSI-X %p vector %d %#08x => %#08lx%s%s\n",
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msix, vector, data, address,
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( ( ctrl & PCI_MSIX_CONTROL_MASK ) ? " (masked)" : "" ),
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( ( pba & ( 1 << vector ) ) ? " (pending)" : "" ) );
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}
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@ -205,6 +205,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define ERRFILE_ena ( ERRFILE_DRIVER | 0x00c90000 )
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#define ERRFILE_icplus ( ERRFILE_DRIVER | 0x00ca0000 )
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#define ERRFILE_intelxl ( ERRFILE_DRIVER | 0x00cb0000 )
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#define ERRFILE_pcimsix ( ERRFILE_DRIVER | 0x00cc0000 )
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#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
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#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )
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@ -94,6 +94,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define PCI_CAP_ID_VPD 0x03 /**< Vital product data */
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#define PCI_CAP_ID_VNDR 0x09 /**< Vendor-specific */
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#define PCI_CAP_ID_EXP 0x10 /**< PCI Express */
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#define PCI_CAP_ID_MSIX 0x11 /**< MSI-X */
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#define PCI_CAP_ID_EA 0x14 /**< Enhanced Allocation */
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/** Next capability */
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@ -109,6 +110,16 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define PCI_EXP_DEVCTL 0x08
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#define PCI_EXP_DEVCTL_FLR 0x8000 /**< Function level reset */
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/** MSI-X interrupts */
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#define PCI_MSIX_CTRL 0x02
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#define PCI_MSIX_CTRL_ENABLE 0x8000 /**< Enable MSI-X */
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#define PCI_MSIX_CTRL_MASK 0x4000 /**< Mask all interrupts */
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#define PCI_MSIX_CTRL_SIZE(x) ( (x) & 0x07ff ) /**< Table size */
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#define PCI_MSIX_DESC_TABLE 0x04
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#define PCI_MSIX_DESC_PBA 0x08
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#define PCI_MSIX_DESC_BIR(x) ( (x) & 0x00000007 ) /**< BAR index */
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#define PCI_MSIX_DESC_OFFSET(x) ( (x) & 0xfffffff8 ) /**< BAR offset */
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/** Uncorrectable error status */
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#define PCI_ERR_UNCOR_STATUS 0x04
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@ -0,0 +1,77 @@
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#ifndef _IPXE_PCIMSIX_H
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#define _IPXE_PCIMSIX_H
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/** @file
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*
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* PCI MSI-X interrupts
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/pci.h>
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/** MSI-X BAR mapped length */
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#define PCI_MSIX_LEN 0x1000
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/** MSI-X vector offset */
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#define PCI_MSIX_VECTOR(n) ( (n) * 0x10 )
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/** MSI-X vector address low 32 bits */
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#define PCI_MSIX_ADDRESS_LO 0x0
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/** MSI-X vector address high 32 bits */
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#define PCI_MSIX_ADDRESS_HI 0x4
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/** MSI-X vector data */
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#define PCI_MSIX_DATA 0x8
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/** MSI-X vector control */
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#define PCI_MSIX_CONTROL 0xc
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#define PCI_MSIX_CONTROL_MASK 0x00000001 /**< Vector is masked */
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/** PCI MSI-X capability */
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struct pci_msix {
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/** Capability offset */
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unsigned int cap;
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/** Number of vectors */
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unsigned int count;
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/** MSI-X table */
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void *table;
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/** Pending bit array */
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void *pba;
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};
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extern int pci_msix_enable ( struct pci_device *pci, struct pci_msix *msix );
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extern void pci_msix_disable ( struct pci_device *pci, struct pci_msix *msix );
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extern void pci_msix_map ( struct pci_msix *msix, unsigned int vector,
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physaddr_t address, uint32_t data );
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extern void pci_msix_control ( struct pci_msix *msix, unsigned int vector,
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uint32_t mask );
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extern void pci_msix_dump ( struct pci_msix *msix, unsigned int vector );
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/**
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* Mask MSI-X interrupt vector
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*
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* @v msix MSI-X capability
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* @v vector MSI-X vector
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*/
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static inline __attribute__ (( always_inline )) void
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pci_msix_mask ( struct pci_msix *msix, unsigned int vector ) {
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pci_msix_control ( msix, vector, PCI_MSIX_CONTROL_MASK );
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}
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/**
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* Unmask MSI-X interrupt vector
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*
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* @v msix MSI-X capability
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* @v vector MSI-X vector
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*/
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static inline __attribute__ (( always_inline )) void
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pci_msix_unmask ( struct pci_msix *msix, unsigned int vector ) {
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pci_msix_control ( msix, vector, 0 );
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}
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#endif /* _IPXE_PCIMSIX_H */
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