mirror of https://github.com/ipxe/ipxe.git
[intel] Add intelxvf driver for Intel 10 GigE virtual function NICs
Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/36/head
Michael Brown
parent
bb1e1048f6
commit
a91b1f7339
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@ -0,0 +1,377 @@
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/*
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* Copyright (C) 2015 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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* You can also choose to distribute this program under the terms of
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* the Unmodified Binary Distribution Licence (as given in the file
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* COPYING.UBDL), provided that you have satisfied its requirements.
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <string.h>
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#include <unistd.h>
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#include <errno.h>
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#include <ipxe/io.h>
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#include <ipxe/pci.h>
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#include <ipxe/netdevice.h>
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#include <ipxe/ethernet.h>
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#include "intelxvf.h"
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/** @file
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*
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* Intel 10 Gigabit Ethernet virtual function network card driver
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*
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*/
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/******************************************************************************
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*
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* Device reset
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*
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******************************************************************************
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*/
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/**
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* Reset hardware
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*
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* @v intel Intel device
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*/
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static void intelxvf_reset ( struct intel_nic *intel ) {
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/* Perform a function-level reset */
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writel ( INTELXVF_CTRL_RST, intel->regs + INTELXVF_CTRL );
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}
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/******************************************************************************
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*
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* Link state
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*
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******************************************************************************
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*/
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/**
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* Check link state
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*
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* @v netdev Network device
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*/
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static void intelxvf_check_link ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t links;
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/* Read link status */
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links = readl ( intel->regs + INTELXVF_LINKS );
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DBGC ( intel, "INTEL %p link status is %08x\n", intel, links );
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/* Update network device */
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if ( links & INTELXVF_LINKS_UP ) {
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netdev_link_up ( netdev );
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} else {
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netdev_link_down ( netdev );
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}
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}
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/******************************************************************************
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*
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* Network device interface
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*
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******************************************************************************
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*/
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/**
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* Open network device
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*
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* @v netdev Network device
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* @ret rc Return status code
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*/
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static int intelxvf_open ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t srrctl;
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uint32_t dca_rxctrl;
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int rc;
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/* Reset the function */
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intelxvf_reset ( intel );
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/* Notify PF that reset is complete */
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if ( ( rc = intelvf_mbox_reset ( intel, NULL ) ) != 0 ) {
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DBGC ( intel, "INTEL %p could not reset: %s\n",
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intel, strerror ( rc ) );
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goto err_mbox_reset;
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}
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/* Set MAC address */
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if ( ( rc = intelvf_mbox_set_mac ( intel, netdev->ll_addr ) ) != 0 ) {
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DBGC ( intel, "INTEL %p could not set MAC address: %s\n",
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intel, strerror ( rc ) );
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goto err_mbox_set_mac;
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}
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/* Create transmit descriptor ring */
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if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
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goto err_create_tx;
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/* Create receive descriptor ring */
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if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
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goto err_create_rx;
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/* Allocate interrupt vectors */
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writel ( ( INTELXVF_IVAR_RX0_DEFAULT | INTELXVF_IVAR_RX0_VALID |
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INTELXVF_IVAR_TX0_DEFAULT | INTELXVF_IVAR_TX0_VALID ),
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intel->regs + INTELXVF_IVAR );
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writel ( ( INTELXVF_IVARM_MBOX_DEFAULT | INTELXVF_IVARM_MBOX_VALID ),
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intel->regs + INTELXVF_IVARM );
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/* Configure receive buffer sizes and set receive descriptor type */
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srrctl = readl ( intel->regs + INTELXVF_SRRCTL );
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srrctl &= ~( INTELXVF_SRRCTL_BSIZE_MASK |
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INTELXVF_SRRCTL_DESCTYPE_MASK );
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srrctl |= ( INTELXVF_SRRCTL_BSIZE_DEFAULT |
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INTELXVF_SRRCTL_DESCTYPE_DEFAULT );
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writel ( srrctl, intel->regs + INTELXVF_SRRCTL );
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/* Clear "must-be-zero" bit for direct cache access (DCA). We
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* leave DCA disabled anyway, but if we do not clear this bit
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* then the received packets contain garbage data.
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*/
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dca_rxctrl = readl ( intel->regs + INTELXVF_DCA_RXCTRL );
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dca_rxctrl &= ~INTELXVF_DCA_RXCTRL_MUST_BE_ZERO;
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writel ( dca_rxctrl, intel->regs + INTELXVF_DCA_RXCTRL );
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/* Fill receive ring */
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intel_refill_rx ( intel );
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/* Update link state */
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intelxvf_check_link ( netdev );
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return 0;
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intel_destroy_ring ( intel, &intel->rx );
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err_create_rx:
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intel_destroy_ring ( intel, &intel->tx );
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err_create_tx:
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err_mbox_set_mac:
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err_mbox_reset:
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intelxvf_reset ( intel );
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return rc;
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}
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/**
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* Close network device
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*
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* @v netdev Network device
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*/
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static void intelxvf_close ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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/* Destroy receive descriptor ring */
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intel_destroy_ring ( intel, &intel->rx );
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/* Discard any unused receive buffers */
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intel_empty_rx ( intel );
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/* Destroy transmit descriptor ring */
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intel_destroy_ring ( intel, &intel->tx );
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/* Reset the function */
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intelxvf_reset ( intel );
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}
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/**
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* Poll for completed and received packets
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*
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* @v netdev Network device
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*/
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static void intelxvf_poll ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t eicr;
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int rc;
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/* Check for and acknowledge interrupts */
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eicr = readl ( intel->regs + INTELXVF_EICR );
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if ( ! eicr )
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return;
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/* Poll for TX completions, if applicable */
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if ( eicr & INTELXVF_EIRQ_TX0 )
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intel_poll_tx ( netdev );
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/* Poll for RX completions, if applicable */
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if ( eicr & INTELXVF_EIRQ_RX0 )
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intel_poll_rx ( netdev );
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/* Poll for mailbox messages, if applicable */
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if ( eicr & INTELXVF_EIRQ_MBOX ) {
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/* Poll mailbox */
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if ( ( rc = intelvf_mbox_poll ( intel ) ) != 0 ) {
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DBGC ( intel, "INTEL %p mailbox poll failed!\n",
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intel );
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netdev_rx_err ( netdev, NULL, rc );
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}
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/* Update link state */
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intelxvf_check_link ( netdev );
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}
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/* Refill RX ring */
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intel_refill_rx ( intel );
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}
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/**
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* Enable or disable interrupts
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*
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* @v netdev Network device
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* @v enable Interrupts should be enabled
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*/
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static void intelxvf_irq ( struct net_device *netdev, int enable ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t mask;
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mask = ( INTELXVF_EIRQ_MBOX | INTELXVF_EIRQ_TX0 | INTELXVF_EIRQ_RX0 );
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if ( enable ) {
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writel ( mask, intel->regs + INTELXVF_EIMS );
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} else {
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writel ( mask, intel->regs + INTELXVF_EIMC );
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}
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}
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/** Network device operations */
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static struct net_device_operations intelxvf_operations = {
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.open = intelxvf_open,
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.close = intelxvf_close,
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.transmit = intel_transmit,
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.poll = intelxvf_poll,
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.irq = intelxvf_irq,
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};
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/******************************************************************************
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*
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* PCI interface
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*
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******************************************************************************
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*/
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/**
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* Probe PCI device
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*
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* @v pci PCI device
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* @ret rc Return status code
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*/
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static int intelxvf_probe ( struct pci_device *pci ) {
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struct net_device *netdev;
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struct intel_nic *intel;
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int rc;
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/* Allocate and initialise net device */
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netdev = alloc_etherdev ( sizeof ( *intel ) );
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if ( ! netdev ) {
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rc = -ENOMEM;
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goto err_alloc;
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}
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netdev_init ( netdev, &intelxvf_operations );
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intel = netdev->priv;
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pci_set_drvdata ( pci, netdev );
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netdev->dev = &pci->dev;
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memset ( intel, 0, sizeof ( *intel ) );
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intel_init_mbox ( &intel->mbox, INTELXVF_MBCTRL, INTELXVF_MBMEM );
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intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTELXVF_TD,
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intel_describe_tx_adv );
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intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTELXVF_RD,
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intel_describe_rx );
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/* Fix up PCI device */
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adjust_pci_device ( pci );
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/* Map registers */
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intel->regs = ioremap ( pci->membase, INTELVF_BAR_SIZE );
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if ( ! intel->regs ) {
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rc = -ENODEV;
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goto err_ioremap;
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}
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/* Reset the function */
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intelxvf_reset ( intel );
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/* Send reset message and fetch MAC address */
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if ( ( rc = intelvf_mbox_reset ( intel, netdev->hw_addr ) ) != 0 ) {
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DBGC ( intel, "INTEL %p could not reset and fetch MAC: %s\n",
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intel, strerror ( rc ) );
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goto err_mbox_reset;
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}
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/* Reset the function (since we will not respond to Control
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* ("ping") mailbox messages until the network device is opened.
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*/
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intelxvf_reset ( intel );
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/* Register network device */
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if ( ( rc = register_netdev ( netdev ) ) != 0 )
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goto err_register_netdev;
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/* Set initial link state */
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intelxvf_check_link ( netdev );
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return 0;
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unregister_netdev ( netdev );
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err_register_netdev:
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err_mbox_reset:
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intelxvf_reset ( intel );
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iounmap ( intel->regs );
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err_ioremap:
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netdev_nullify ( netdev );
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netdev_put ( netdev );
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err_alloc:
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return rc;
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}
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/**
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* Remove PCI device
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*
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* @v pci PCI device
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*/
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static void intelxvf_remove ( struct pci_device *pci ) {
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struct net_device *netdev = pci_get_drvdata ( pci );
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struct intel_nic *intel = netdev->priv;
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/* Unregister network device */
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unregister_netdev ( netdev );
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/* Reset the NIC */
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intelxvf_reset ( intel );
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/* Free network device */
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iounmap ( intel->regs );
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netdev_nullify ( netdev );
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netdev_put ( netdev );
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}
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/** PCI device IDs */
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static struct pci_device_id intelxvf_nics[] = {
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PCI_ROM ( 0x8086, 0x10ed, "82599-vf", "82599 VF", 0 ),
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PCI_ROM ( 0x8086, 0x1515, "x540-vf", "X540 VF", 0 ),
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PCI_ROM ( 0x8086, 0x1565, "x550-vf", "X550 VF", 0 ),
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PCI_ROM ( 0x8086, 0x15a8, "x552-vf", "X552 VF", 0 ),
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};
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/** PCI driver */
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struct pci_driver intelxvf_driver __pci_driver = {
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.ids = intelxvf_nics,
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.id_count = ( sizeof ( intelxvf_nics ) / sizeof ( intelxvf_nics[0] ) ),
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.probe = intelxvf_probe,
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.remove = intelxvf_remove,
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};
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@ -0,0 +1,77 @@
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#ifndef _INTELXVF_H
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#define _INTELXVF_H
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/** @file
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*
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* Intel 10 Gigabit Ethernet virtual function network card driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include "intelvf.h"
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/** Control Register */
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#define INTELXVF_CTRL 0x0000UL
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#define INTELXVF_CTRL_RST 0x04000000UL /**< Function-level reset */
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/** Link Status Register */
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#define INTELXVF_LINKS 0x0010UL
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#define INTELXVF_LINKS_UP 0x40000000UL /**< Link up */
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/** Extended Interrupt Cause Read Register */
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#define INTELXVF_EICR 0x0100UL
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#define INTELXVF_EIRQ_RX0 0x00000001UL /**< RX queue 0 (via IVAR) */
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#define INTELXVF_EIRQ_TX0 0x00000002UL /**< TX queue 0 (via IVAR) */
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#define INTELXVF_EIRQ_MBOX 0x00000004UL /**< Mailbox (via IVARM) */
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/** Extended Interrupt Mask Set/Read Register */
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#define INTELXVF_EIMS 0x0108UL
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/** Extended Interrupt Mask Clear Register */
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#define INTELXVF_EIMC 0x010cUL
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/** Interrupt Vector Allocation Register */
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#define INTELXVF_IVAR 0x0120UL
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#define INTELXVF_IVAR_RX0(bit) ( (bit) << 0 ) /**< RX queue 0 allocation */
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#define INTELXVF_IVAR_RX0_DEFAULT INTELXVF_IVAR_RX0 ( 0x00 )
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#define INTELXVF_IVAR_RX0_MASK INTELXVF_IVAR_RX0 ( 0x01 )
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#define INTELXVF_IVAR_RX0_VALID 0x00000080UL /**< RX queue 0 valid */
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#define INTELXVF_IVAR_TX0(bit) ( (bit) << 8 ) /**< TX queue 0 allocation */
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#define INTELXVF_IVAR_TX0_DEFAULT INTELXVF_IVAR_TX0 ( 0x01 )
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#define INTELXVF_IVAR_TX0_MASK INTELXVF_IVAR_TX0 ( 0x01 )
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#define INTELXVF_IVAR_TX0_VALID 0x00008000UL /**< TX queue 0 valid */
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/** Interrupt Vector Allocation Miscellaneous Register */
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#define INTELXVF_IVARM 0x0140UL
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#define INTELXVF_IVARM_MBOX(bit) ( (bit) << 0 ) /**< Mailbox allocation */
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#define INTELXVF_IVARM_MBOX_DEFAULT INTELXVF_IVARM_MBOX ( 0x02 )
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#define INTELXVF_IVARM_MBOX_MASK INTELXVF_IVARM_MBOX ( 0x03 )
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#define INTELXVF_IVARM_MBOX_VALID 0x00000080UL /**< Mailbox valid */
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/** Mailbox Memory Register Base */
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#define INTELXVF_MBMEM 0x0200UL
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/** Mailbox Control Register */
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#define INTELXVF_MBCTRL 0x02fcUL
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/** Receive Descriptor register block */
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#define INTELXVF_RD 0x1000UL
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/** RX DCA Control Register */
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#define INTELXVF_DCA_RXCTRL 0x100cUL
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#define INTELXVF_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL /**< Must be zero */
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/** Split Receive Control Register */
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#define INTELXVF_SRRCTL 0x1014UL
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#define INTELXVF_SRRCTL_BSIZE(kb) ( (kb) << 0 ) /**< Receive buffer size */
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#define INTELXVF_SRRCTL_BSIZE_DEFAULT INTELXVF_SRRCTL_BSIZE ( 0x02 )
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#define INTELXVF_SRRCTL_BSIZE_MASK INTELXVF_SRRCTL_BSIZE ( 0x1f )
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#define INTELXVF_SRRCTL_DESCTYPE(typ) ( (typ) << 25 ) /**< Descriptor type */
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#define INTELXVF_SRRCTL_DESCTYPE_DEFAULT INTELXVF_SRRCTL_DESCTYPE ( 0x00 )
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#define INTELXVF_SRRCTL_DESCTYPE_MASK INTELXVF_SRRCTL_DESCTYPE ( 0x07 )
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/** Transmit Descriptor register block */
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#define INTELXVF_TD 0x2000UL
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#endif /* _INTELXVF_H */
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@ -178,6 +178,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define ERRFILE_qib7322 ( ERRFILE_DRIVER | 0x00760000 )
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#define ERRFILE_smsc75xx ( ERRFILE_DRIVER | 0x00770000 )
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#define ERRFILE_intelvf ( ERRFILE_DRIVER | 0x00780000 )
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#define ERRFILE_intelxvf ( ERRFILE_DRIVER | 0x00790000 )
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#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
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#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )
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