mirror of https://github.com/ipxe/ipxe.git
[intelxl] Allow for arbitrary placement of ring tail registers
The virtual function transmit and receive ring tail register offsets do not match those of the physical function. Allow the tail register offsets to be specified separately. Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/92/head
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f460a436ca
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9907fd54d3
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@ -1096,7 +1096,6 @@ static int intelxl_disable_ring ( struct intelxl_nic *intelxl,
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*/
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static int intelxl_create_ring ( struct intelxl_nic *intelxl,
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struct intelxl_ring *ring ) {
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void *ring_regs = ( intelxl->regs + ring->reg );
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physaddr_t address;
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int rc;
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@ -1111,7 +1110,7 @@ static int intelxl_create_ring ( struct intelxl_nic *intelxl,
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memset ( ring->desc.raw, 0, ring->len );
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/* Reset tail pointer */
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writel ( 0, ( ring_regs + INTELXL_QXX_TAIL ) );
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writel ( 0, ( intelxl->regs + ring->tail ) );
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/* Program queue context */
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address = virt_to_bus ( ring->desc.raw );
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@ -1127,7 +1126,8 @@ static int intelxl_create_ring ( struct intelxl_nic *intelxl,
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ring->cons = 0;
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DBGC ( intelxl, "INTELXL %p ring %06x is at [%08llx,%08llx)\n",
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intelxl, ring->reg, ( ( unsigned long long ) address ),
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intelxl, ( ring->reg + ring->tail ),
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( ( unsigned long long ) address ),
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( ( unsigned long long ) address + ring->len ) );
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return 0;
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@ -1207,8 +1207,7 @@ static void intelxl_refill_rx ( struct intelxl_nic *intelxl ) {
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if ( refilled ) {
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wmb();
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rx_tail = ( intelxl->rx.prod % INTELXL_RX_NUM_DESC );
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writel ( rx_tail,
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( intelxl->regs + intelxl->rx.reg + INTELXL_QXX_TAIL));
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writel ( rx_tail, ( intelxl->regs + intelxl->rx.tail ) );
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}
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}
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@ -1363,8 +1362,7 @@ static int intelxl_transmit ( struct net_device *netdev,
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wmb();
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/* Notify card that there are packets ready to transmit */
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writel ( tx_tail,
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( intelxl->regs + intelxl->tx.reg + INTELXL_QXX_TAIL ) );
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writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
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DBGC2 ( intelxl, "INTELXL %p TX %d is [%llx,%llx)\n", intelxl, tx_idx,
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( ( unsigned long long ) address ),
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@ -1595,7 +1593,9 @@ static int intelxl_probe ( struct pci_device *pci ) {
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/* Configure queue register addresses */
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intelxl->tx.reg = INTELXL_QTX ( intelxl->queue );
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intelxl->tx.tail = ( intelxl->tx.reg + INTELXL_QXX_TAIL );
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intelxl->rx.reg = INTELXL_QRX ( intelxl->queue );
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intelxl->rx.tail = ( intelxl->rx.reg + INTELXL_QXX_TAIL );
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/* Configure interrupt causes */
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writel ( ( INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE |
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@ -680,6 +680,8 @@ struct intelxl_ring {
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/** Register block */
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unsigned int reg;
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/** Tail register */
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unsigned int tail;
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/** Length (in bytes) */
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size_t len;
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/** Program queue context
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