mirror of https://github.com/ipxe/ipxe.git
[ehci] Add support for EHCI host controllers
Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/35/head
Michael Brown
parent
ec0e2a7bd7
commit
8370f87745
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@ -37,3 +37,6 @@ PROVIDE_REQUIRING_SYMBOL();
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#ifdef USB_HCD_XHCI
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REQUIRE_OBJECT ( xhci );
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#endif
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#ifdef USB_HCD_EHCI
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REQUIRE_OBJECT ( ehci );
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#endif
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@ -37,6 +37,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define SANBOOT_PROTO_FCP /* Fibre Channel protocol */
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#define USB_HCD_XHCI /* xHCI USB host controller */
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#define USB_HCD_EHCI /* EHCI USB host controller */
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#define REBOOT_CMD /* Reboot command */
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#define CPUID_CMD /* x86 CPU feature detection command */
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@ -16,6 +16,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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*
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*/
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//#undef USB_HCD_XHCI /* xHCI USB host controller */
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//#undef USB_HCD_EHCI /* EHCI USB host controller */
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#include <config/named.h>
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#include NAMED_CONFIG(usb.h)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,516 @@
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#ifndef _IPXE_EHCI_H
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#define _IPXE_EHCI_H
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/** @file
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*
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* USB Enhanced Host Controller Interface (EHCI) driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/pci.h>
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#include <ipxe/usb.h>
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/** Minimum alignment required for data structures
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*
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* With the exception of the periodic frame list (which is
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* page-aligned), data structures used by EHCI generally require
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* 32-byte alignment and must not cross a 4kB page boundary. We
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* simplify this requirement by aligning each structure on its own
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* size, with a minimum of a 32 byte alignment.
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*/
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#define EHCI_MIN_ALIGN 32
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/** Maximum transfer size
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*
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* EHCI allows for transfers of up to 20kB with page-alignment, or
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* 16kB with arbitrary alignment.
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*/
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#define EHCI_MTU 16384
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/** Page-alignment required for some data structures */
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#define EHCI_PAGE_ALIGN 4096
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/** EHCI PCI BAR */
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#define EHCI_BAR PCI_BASE_ADDRESS_0
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/** Capability register length */
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#define EHCI_CAP_CAPLENGTH 0x00
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/** Host controller interface version number */
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#define EHCI_CAP_HCIVERSION 0x02
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/** Structural parameters */
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#define EHCI_CAP_HCSPARAMS 0x04
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/** Number of ports */
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#define EHCI_HCSPARAMS_PORTS(params) ( ( (params) >> 0 ) & 0x0f )
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/** Capability parameters */
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#define EHCI_CAP_HCCPARAMS 0x08
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/** 64-bit addressing capability */
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#define EHCI_HCCPARAMS_ADDR64(params) ( ( (params) >> 0 ) & 0x1 )
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/** Programmable frame list flag */
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#define EHCI_HCCPARAMS_FLSIZE(params) ( ( (params) >> 1 ) & 0x1 )
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/** EHCI extended capabilities pointer */
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#define EHCI_HCCPARAMS_EECP(params) ( ( ( (params) >> 8 ) & 0xff ) )
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/** EHCI extended capability ID */
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#define EHCI_EECP_ID(eecp) ( ( (eecp) >> 0 ) & 0xff )
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/** Next EHCI extended capability pointer */
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#define EHCI_EECP_NEXT(eecp) ( ( ( (eecp) >> 8 ) & 0xff ) )
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/** USB legacy support extended capability */
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#define EHCI_EECP_ID_LEGACY 1
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/** USB legacy support BIOS owned semaphore */
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#define EHCI_USBLEGSUP_BIOS 0x02
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/** USB legacy support BIOS ownership flag */
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#define EHCI_USBLEGSUP_BIOS_OWNED 0x01
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/** USB legacy support OS owned semaphore */
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#define EHCI_USBLEGSUP_OS 0x03
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/** USB legacy support OS ownership flag */
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#define EHCI_USBLEGSUP_OS_OWNED 0x01
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/** USB legacy support control/status */
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#define EHCI_USBLEGSUP_CTLSTS 0x04
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/** USB command register */
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#define EHCI_OP_USBCMD 0x00
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/** Run/stop */
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#define EHCI_USBCMD_RUN 0x00000001UL
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/** Host controller reset */
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#define EHCI_USBCMD_HCRST 0x00000002UL
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/** Frame list size */
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#define EHCI_USBCMD_FLSIZE(flsize) ( (flsize) << 2 )
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/** Frame list size mask */
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#define EHCI_USBCMD_FLSIZE_MASK EHCI_USBCMD_FLSIZE ( 3 )
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/** Default frame list size */
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#define EHCI_FLSIZE_DEFAULT 0
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/** Smallest allowed frame list size */
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#define EHCI_FLSIZE_SMALL 2
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/** Number of elements in frame list */
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#define EHCI_PERIODIC_FRAMES(flsize) ( 1024 >> (flsize) )
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/** Periodic schedule enable */
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#define EHCI_USBCMD_PERIODIC 0x00000010UL
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/** Asynchronous schedule enable */
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#define EHCI_USBCMD_ASYNC 0x00000020UL
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/** Asyncchronous schedule advance doorbell */
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#define EHCI_USBCMD_ASYNC_ADVANCE 0x000040UL
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/** USB status register */
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#define EHCI_OP_USBSTS 0x04
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/** USB interrupt */
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#define EHCI_USBSTS_USBINT 0x00000001UL
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/** USB error interrupt */
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#define EHCI_USBSTS_USBERRINT 0x00000002UL
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/** Port change detect */
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#define EHCI_USBSTS_PORT 0x00000004UL
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/** Frame list rollover */
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#define EHCI_USBSTS_ROLLOVER 0x00000008UL
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/** Host system error */
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#define EHCI_USBSTS_SYSERR 0x00000010UL
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/** Asynchronous schedule advanced */
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#define EHCI_USBSTS_ASYNC_ADVANCE 0x00000020UL
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/** Periodic schedule enabled */
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#define EHCI_USBSTS_PERIODIC 0x00004000UL
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/** Asynchronous schedule enabled */
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#define EHCI_USBSTS_ASYNC 0x00008000UL
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/** Host controller halted */
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#define EHCI_USBSTS_HCH 0x00001000UL
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/** USB status change mask */
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#define EHCI_USBSTS_CHANGE \
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( EHCI_USBSTS_USBINT | EHCI_USBSTS_USBERRINT | \
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EHCI_USBSTS_PORT | EHCI_USBSTS_ROLLOVER | \
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EHCI_USBSTS_SYSERR | EHCI_USBSTS_ASYNC_ADVANCE )
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/** USB interrupt enable register */
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#define EHCI_OP_USBINTR 0x08
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/** Frame index register */
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#define EHCI_OP_FRINDEX 0x0c
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/** Control data structure segment register */
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#define EHCI_OP_CTRLDSSEGMENT 0x10
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/** Periodic frame list base address register */
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#define EHCI_OP_PERIODICLISTBASE 0x14
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/** Current asynchronous list address register */
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#define EHCI_OP_ASYNCLISTADDR 0x18
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/** Configure flag register */
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#define EHCI_OP_CONFIGFLAG 0x40
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/** Configure flag */
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#define EHCI_CONFIGFLAG_CF 0x00000001UL
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/** Port status and control register */
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#define EHCI_OP_PORTSC(port) ( 0x40 + ( (port) << 2 ) )
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/** Current connect status */
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#define EHCI_PORTSC_CCS 0x00000001UL
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/** Connect status change */
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#define EHCI_PORTSC_CSC 0x00000002UL
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/** Port enabled */
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#define EHCI_PORTSC_PED 0x00000004UL
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/** Port enabled/disabled change */
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#define EHCI_PORTSC_PEC 0x00000008UL
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/** Over-current change */
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#define EHCI_PORTSC_OCC 0x00000020UL
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/** Port reset */
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#define EHCI_PORTSC_PR 0x00000100UL
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/** Line status */
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#define EHCI_PORTSC_LINE_STATUS(portsc) ( ( (portsc) >> 10 ) & 0x3 )
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/** Line status: low-speed device */
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#define EHCI_PORTSC_LINE_STATUS_LOW 0x1
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/** Port power */
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#define EHCI_PORTSC_PP 0x00001000UL
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/** Port owner */
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#define EHCI_PORTSC_OWNER 0x00002000UL
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/** Port status change mask */
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#define EHCI_PORTSC_CHANGE \
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( EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | EHCI_PORTSC_OCC )
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/** List terminator */
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#define EHCI_LINK_TERMINATE 0x00000001UL
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/** Frame list type */
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#define EHCI_LINK_TYPE(type) ( (type) << 1 )
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/** Queue head type */
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#define EHCI_LINK_TYPE_QH EHCI_LINK_TYPE ( 1 )
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/** A periodic frame list entry */
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struct ehci_periodic_frame {
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/** First queue head */
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uint32_t link;
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} __attribute__ (( packed ));
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/** A transfer descriptor */
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struct ehci_transfer_descriptor {
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/** Next transfer descriptor */
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uint32_t next;
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/** Alternate next transfer descriptor */
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uint32_t alt;
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/** Status */
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uint8_t status;
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/** Flags */
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uint8_t flags;
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/** Transfer length */
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uint16_t len;
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/** Buffer pointers (low 32 bits) */
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uint32_t low[5];
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/** Extended buffer pointers (high 32 bits) */
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uint32_t high[5];
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/** Immediate data buffer
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*
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* This is not part of the hardware data structure. Transfer
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* descriptors must be aligned to a 32-byte boundary. Create
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* an array of descriptors therefore requires 12 bytes of
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* padding at the end of each descriptor.
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*
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* We can use this padding as an immediate data buffer (for
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* setup packets). This avoids the need for separate
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* allocations. As a bonus, there is no need to check this
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* buffer for reachability, since it is contained within a
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* transfer descriptor which must already be reachable.
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*/
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uint8_t immediate[12];
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} __attribute__ (( packed ));
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/** Transaction error */
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#define EHCI_STATUS_XACT_ERR 0x08
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/** Babble detected */
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#define EHCI_STATUS_BABBLE 0x10
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/** Data buffer error */
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#define EHCI_STATUS_BUFFER 0x20
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/** Halted */
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#define EHCI_STATUS_HALTED 0x40
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/** Active */
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#define EHCI_STATUS_ACTIVE 0x80
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/** PID code */
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#define EHCI_FL_PID(code) ( (code) << 0 )
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/** OUT token */
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#define EHCI_FL_PID_OUT EHCI_FL_PID ( 0 )
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/** IN token */
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#define EHCI_FL_PID_IN EHCI_FL_PID ( 1 )
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/** SETUP token */
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#define EHCI_FL_PID_SETUP EHCI_FL_PID ( 2 )
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/** Interrupt on completion */
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#define EHCI_FL_IOC 0x80
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/** Length mask */
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#define EHCI_LEN_MASK 0x7fff
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/** Data toggle */
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#define EHCI_LEN_TOGGLE 0x8000
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/** A queue head */
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struct ehci_queue_head {
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/** Horizontal link pointer */
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uint32_t link;
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/** Endpoint characteristics */
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uint32_t chr;
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/** Endpoint capabilities */
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uint32_t cap;
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/** Current transfer descriptor */
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uint32_t current;
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/** Transfer descriptor cache */
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struct ehci_transfer_descriptor cache;
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} __attribute__ (( packed ));
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/** Device address */
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#define EHCI_CHR_ADDRESS( address ) ( (address) << 0 )
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/** Endpoint number */
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#define EHCI_CHR_ENDPOINT( address ) ( ( (address) & 0xf ) << 8 )
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/** Endpoint speed */
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#define EHCI_CHR_EPS( eps ) ( (eps) << 12 )
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/** Full-speed endpoint */
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#define EHCI_CHR_EPS_FULL EHCI_CHR_EPS ( 0 )
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/** Low-speed endpoint */
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#define EHCI_CHR_EPS_LOW EHCI_CHR_EPS ( 1 )
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/** High-speed endpoint */
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#define EHCI_CHR_EPS_HIGH EHCI_CHR_EPS ( 2 )
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/** Explicit data toggles */
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#define EHCI_CHR_TOGGLE 0x00004000UL
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/** Head of reclamation list flag */
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#define EHCI_CHR_HEAD 0x00008000UL
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/** Maximum packet length */
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#define EHCI_CHR_MAX_LEN( len ) ( (len) << 16 )
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/** Control endpoint flag */
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#define EHCI_CHR_CONTROL 0x08000000UL
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/** Interrupt schedule mask */
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#define EHCI_CAP_INTR_SCHED( uframe ) ( 1 << ( (uframe) + 0 ) )
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/** High-bandwidth pipe multiplier */
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#define EHCI_CAP_MULT( mult ) ( (mult) << 30 )
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/** A transfer descriptor ring */
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struct ehci_ring {
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/** Producer counter */
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unsigned int prod;
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/** Consumer counter */
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unsigned int cons;
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/** Residual untransferred data */
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size_t residual;
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/** I/O buffers */
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struct io_buffer **iobuf;
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/** Queue head */
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struct ehci_queue_head *head;
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/** Transfer descriptors */
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struct ehci_transfer_descriptor *desc;
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};
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/** Number of transfer descriptors in a ring
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*
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* This is a policy decision.
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*/
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#define EHCI_RING_COUNT 64
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/**
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* Calculate space used in transfer descriptor ring
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*
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* @v ring Transfer descriptor ring
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* @ret fill Number of entries used
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*/
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static inline __attribute__ (( always_inline )) unsigned int
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ehci_ring_fill ( struct ehci_ring *ring ) {
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unsigned int fill;
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fill = ( ring->prod - ring->cons );
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assert ( fill <= EHCI_RING_COUNT );
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return fill;
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}
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/**
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* Calculate space remaining in transfer descriptor ring
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*
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* @v ring Transfer descriptor ring
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* @ret remaining Number of entries remaining
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*/
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static inline __attribute__ (( always_inline )) unsigned int
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ehci_ring_remaining ( struct ehci_ring *ring ) {
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unsigned int fill = ehci_ring_fill ( ring );
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return ( EHCI_RING_COUNT - fill );
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}
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/** Time to delay after enabling power to a port
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*
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* This is not mandated by EHCI; we use the value given for xHCI.
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*/
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#define EHCI_PORT_POWER_DELAY_MS 20
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/** Maximum time to wait for BIOS to release ownership
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*
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* This is a policy decision.
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*/
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#define EHCI_USBLEGSUP_MAX_WAIT_MS 100
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/** Maximum time to wait for asynchronous schedule to advance
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*
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* This is a policy decision.
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*/
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#define EHCI_ASYNC_ADVANCE_MAX_WAIT_MS 100
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/** Maximum time to wait for host controller to stop
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*
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* This is a policy decision.
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*/
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#define EHCI_STOP_MAX_WAIT_MS 100
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/** Maximum time to wait for reset to complete
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*
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* This is a policy decision.
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*/
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#define EHCI_RESET_MAX_WAIT_MS 500
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/** Maximum time to wait for a port reset to complete
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*
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* This is a policy decision.
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*/
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#define EHCI_PORT_RESET_MAX_WAIT_MS 500
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/** An EHCI transfer */
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struct ehci_transfer {
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/** Data buffer */
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void *data;
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/** Length */
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size_t len;
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/** Flags
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*
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* This is the bitwise OR of zero or more EHCI_FL_XXX values.
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* The low 8 bits are copied to the flags byte within the
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* transfer descriptor; the remaining bits hold flags
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* meaningful only to our driver code.
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*/
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unsigned int flags;
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};
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/** Copy data to immediate data buffer */
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#define EHCI_FL_IMMEDIATE 0x0100
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/** Set initial data toggle */
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#define EHCI_FL_TOGGLE 0x8000
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/** An EHCI device */
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struct ehci_device {
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/** Registers */
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void *regs;
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/** Capability registers */
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void *cap;
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/** Operational registers */
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void *op;
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/** Number of ports */
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unsigned int ports;
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/** 64-bit addressing capability */
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int addr64;
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/** Frame list size */
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unsigned int flsize;
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/** EHCI extended capabilities offset */
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unsigned int eecp;
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/** USB legacy support capability (if present and enabled) */
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unsigned int legacy;
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|
||||
/** Control data structure segment */
|
||||
uint32_t ctrldssegment;
|
||||
/** Asynchronous queue head */
|
||||
struct ehci_queue_head *head;
|
||||
/** Periodic frame list */
|
||||
struct ehci_periodic_frame *frame;
|
||||
|
||||
/** List of all endpoints */
|
||||
struct list_head endpoints;
|
||||
/** Asynchronous schedule */
|
||||
struct list_head async;
|
||||
/** Periodic schedule
|
||||
*
|
||||
* Listed in decreasing order of endpoint interval.
|
||||
*/
|
||||
struct list_head periodic;
|
||||
|
||||
/** USB bus */
|
||||
struct usb_bus *bus;
|
||||
};
|
||||
|
||||
/** An EHCI endpoint */
|
||||
struct ehci_endpoint {
|
||||
/** EHCI device */
|
||||
struct ehci_device *ehci;
|
||||
/** USB endpoint */
|
||||
struct usb_endpoint *ep;
|
||||
/** List of all endpoints */
|
||||
struct list_head list;
|
||||
/** Endpoint schedule */
|
||||
struct list_head schedule;
|
||||
|
||||
/** Transfer descriptor ring */
|
||||
struct ehci_ring ring;
|
||||
};
|
||||
|
||||
#endif /* _IPXE_EHCI_H */
|
||||
|
|
@ -79,6 +79,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
|
|||
#define ERRFILE_usb ( ERRFILE_DRIVER | 0x00070000 )
|
||||
#define ERRFILE_usbhub ( ERRFILE_DRIVER | 0x00080000 )
|
||||
#define ERRFILE_xhci ( ERRFILE_DRIVER | 0x00090000 )
|
||||
#define ERRFILE_ehci ( ERRFILE_DRIVER | 0x000a0000 )
|
||||
|
||||
#define ERRFILE_nvs ( ERRFILE_DRIVER | 0x00100000 )
|
||||
#define ERRFILE_spi ( ERRFILE_DRIVER | 0x00110000 )
|
||||
|
|
|
|||
|
|
@ -1178,6 +1178,9 @@ extern unsigned int usb_route_string ( struct usb_device *usb );
|
|||
extern unsigned int usb_depth ( struct usb_device *usb );
|
||||
extern struct usb_port * usb_root_hub_port ( struct usb_device *usb );
|
||||
|
||||
/** Minimum reset time */
|
||||
#define USB_RESET_DELAY_MS 50
|
||||
|
||||
/** Maximum time to wait for a control transaction to complete
|
||||
*
|
||||
* This is a policy decision.
|
||||
|
|
|
|||
Loading…
Reference in New Issue