mirror of https://github.com/ipxe/ipxe.git
[ena] Add driver for Amazon ENA virtual function NIC
Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/68/head
Michael Brown
parent
2bb4ec1f54
commit
2fb70e8b32
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#ifndef _ENA_H
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#define _ENA_H
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/** @file
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*
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* Amazon ENA network driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/if_ether.h>
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/** BAR size */
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#define ENA_BAR_SIZE 16384
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/** Queue alignment */
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#define ENA_ALIGN 4096
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/** Number of admin queue entries */
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#define ENA_AQ_COUNT 2
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/** Number of admin completion queue entries */
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#define ENA_ACQ_COUNT 2
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/** Number of transmit queue entries */
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#define ENA_TX_COUNT 16
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/** Number of receive queue entries */
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#define ENA_RX_COUNT 16
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/** Base address low register offset */
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#define ENA_BASE_LO 0x0
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/** Base address high register offset */
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#define ENA_BASE_HI 0x4
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/** Capability register value */
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#define ENA_CAPS( count, size ) ( ( (size) << 16 ) | ( (count) << 0 ) )
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/** Admin queue base address register */
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#define ENA_AQ_BASE 0x10
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/** Admin queue capabilities register */
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#define ENA_AQ_CAPS 0x18
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/** Admin completion queue base address register */
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#define ENA_ACQ_BASE 0x20
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/** Admin completion queue capabilities register */
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#define ENA_ACQ_CAPS 0x28
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/** Admin queue doorbell register */
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#define ENA_AQ_DB 0x2c
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/** Maximum time to wait for admin requests */
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#define ENA_ADMIN_MAX_WAIT_MS 5000
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/** Device control register */
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#define ENA_CTRL 0x54
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#define ENA_CTRL_RESET 0x00000001UL /**< Reset */
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/** Maximum time to wait for reset */
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#define ENA_RESET_MAX_WAIT_MS 1000
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/** Device status register */
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#define ENA_STAT 0x58
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#define ENA_STAT_READY 0x00000001UL /**< Ready */
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/** Admin queue entry header */
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struct ena_aq_header {
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/** Request identifier */
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uint8_t id;
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/** Reserved */
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uint8_t reserved;
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/** Opcode */
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uint8_t opcode;
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/** Flags */
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uint8_t flags;
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} __attribute__ (( packed ));
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/** Admin queue ownership phase flag */
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#define ENA_AQ_PHASE 0x01
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/** Admin completion queue entry header */
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struct ena_acq_header {
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/** Request identifier */
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uint8_t id;
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/** Reserved */
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uint8_t reserved;
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/** Status */
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uint8_t status;
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/** Flags */
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uint8_t flags;
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/** Extended status */
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uint16_t ext;
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/** Consumer index */
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uint16_t cons;
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} __attribute__ (( packed ));
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/** Admin completion queue ownership phase flag */
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#define ENA_ACQ_PHASE 0x01
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/** Device attributes */
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#define ENA_DEVICE_ATTRIBUTES 1
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/** Device attributes */
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struct ena_device_attributes {
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/** Implementation */
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uint32_t implementation;
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/** Device version */
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uint32_t version;
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/** Supported features */
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uint32_t features;
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/** Reserved */
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uint8_t reserved_a[4];
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/** Physical address width */
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uint32_t physical;
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/** Virtual address width */
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uint32_t virtual;
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/** MAC address */
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uint8_t mac[ETH_ALEN];
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/** Reserved */
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uint8_t reserved_b[2];
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/** Maximum MTU */
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uint32_t mtu;
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} __attribute__ (( packed ));
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/** Feature */
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union ena_feature {
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/** Device attributes */
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struct ena_device_attributes device;
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};
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/** Submission queue direction */
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enum ena_sq_direction {
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/** Transmit */
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ENA_SQ_TX = 0x20,
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/** Receive */
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ENA_SQ_RX = 0x40,
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};
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/** Create submission queue */
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#define ENA_CREATE_SQ 1
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/** Create submission queue request */
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struct ena_create_sq_req {
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/** Header */
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struct ena_aq_header header;
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/** Direction */
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uint8_t direction;
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/** Reserved */
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uint8_t reserved_a;
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/** Policy */
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uint16_t policy;
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/** Completion queue identifier */
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uint16_t cq_id;
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/** Number of entries */
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uint16_t count;
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/** Base address */
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uint64_t address;
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/** Writeback address */
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uint64_t writeback;
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/** Reserved */
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uint8_t reserved_b[8];
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} __attribute__ (( packed ));
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/** Submission queue policy */
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enum ena_sq_policy {
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/** Use host memory */
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ENA_SQ_HOST_MEMORY = 0x0001,
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/** Memory is contiguous */
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ENA_SQ_CONTIGUOUS = 0x0100,
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};
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/** Create submission queue response */
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struct ena_create_sq_rsp {
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/** Header */
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struct ena_acq_header header;
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/** Submission queue identifier */
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uint16_t id;
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/** Reserved */
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uint8_t reserved[2];
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/** Doorbell register offset */
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uint32_t doorbell;
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/** LLQ descriptor ring offset */
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uint32_t llq_desc;
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/** LLQ header offset */
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uint32_t llq_data;
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} __attribute__ (( packed ));
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/** Destroy submission queue */
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#define ENA_DESTROY_SQ 2
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/** Destroy submission queue request */
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struct ena_destroy_sq_req {
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/** Header */
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struct ena_aq_header header;
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/** Submission queue identifier */
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uint16_t id;
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/** Direction */
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uint8_t direction;
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/** Reserved */
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uint8_t reserved;
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} __attribute__ (( packed ));
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/** Destroy submission queue response */
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struct ena_destroy_sq_rsp {
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/** Header */
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struct ena_acq_header header;
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} __attribute__ (( packed ));
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/** Create completion queue */
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#define ENA_CREATE_CQ 3
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/** Create completion queue request */
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struct ena_create_cq_req {
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/** Header */
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struct ena_aq_header header;
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/** Interrupts enabled */
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uint8_t intr;
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/** Entry size (in 32-bit words) */
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uint8_t size;
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/** Number of entries */
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uint16_t count;
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/** MSI-X vector */
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uint32_t vector;
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/** Base address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Create completion queue response */
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struct ena_create_cq_rsp {
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/** Header */
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struct ena_acq_header header;
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/** Completion queue identifier */
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uint16_t id;
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/** Actual number of entries */
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uint16_t count;
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/** NUMA node register offset */
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uint32_t node;
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/** Doorbell register offset */
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uint32_t doorbell;
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/** Interrupt unmask register offset */
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uint32_t intr;
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} __attribute__ (( packed ));
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/** Destroy completion queue */
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#define ENA_DESTROY_CQ 4
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/** Destroy completion queue request */
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struct ena_destroy_cq_req {
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/** Header */
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struct ena_aq_header header;
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/** Completion queue identifier */
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uint16_t id;
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/** Reserved */
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uint8_t reserved[2];
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} __attribute__ (( packed ));
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/** Destroy completion queue response */
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struct ena_destroy_cq_rsp {
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/** Header */
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struct ena_acq_header header;
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} __attribute__ (( packed ));
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/** Get feature */
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#define ENA_GET_FEATURE 8
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/** Get feature request */
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struct ena_get_feature_req {
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/** Header */
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struct ena_aq_header header;
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/** Length */
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uint32_t len;
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/** Address */
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uint64_t address;
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/** Flags */
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uint8_t flags;
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/** Feature identifier */
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uint8_t id;
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/** Reserved */
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uint8_t reserved[2];
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} __attribute__ (( packed ));
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/** Get feature response */
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struct ena_get_feature_rsp {
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/** Header */
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struct ena_acq_header header;
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/** Feature */
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union ena_feature feature;
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} __attribute__ (( packed ));
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/** Get statistics */
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#define ENA_GET_STATS 11
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/** Get statistics request */
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struct ena_get_stats_req {
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/** Header */
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struct ena_aq_header header;
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/** Reserved */
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uint8_t reserved_a[12];
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/** Type */
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uint8_t type;
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/** Scope */
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uint8_t scope;
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/** Reserved */
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uint8_t reserved_b[2];
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/** Queue ID */
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uint16_t queue;
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/** Device ID */
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uint16_t device;
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} __attribute__ (( packed ));
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/** Basic statistics */
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#define ENA_STATS_TYPE_BASIC 0
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/** Ethernet statistics */
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#define ENA_STATS_SCOPE_ETH 1
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/** My device */
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#define ENA_DEVICE_MINE 0xffff
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/** Get statistics response */
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struct ena_get_stats_rsp {
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/** Header */
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struct ena_acq_header header;
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/** Transmit byte count */
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uint64_t tx_bytes;
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/** Transmit packet count */
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uint64_t tx_packets;
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/** Receive byte count */
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uint64_t rx_bytes;
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/** Receive packet count */
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uint64_t rx_packets;
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/** Receive drop count */
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uint64_t rx_drops;
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} __attribute__ (( packed ));
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/** Admin queue request */
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union ena_aq_req {
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/** Header */
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struct ena_aq_header header;
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/** Create submission queue */
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struct ena_create_sq_req create_sq;
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/** Destroy submission queue */
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struct ena_destroy_sq_req destroy_sq;
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/** Create completion queue */
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struct ena_create_cq_req create_cq;
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/** Destroy completion queue */
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struct ena_destroy_cq_req destroy_cq;
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/** Get feature */
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struct ena_get_feature_req get_feature;
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/** Get statistics */
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struct ena_get_stats_req get_stats;
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/** Padding */
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uint8_t pad[64];
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};
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/** Admin completion queue response */
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union ena_acq_rsp {
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/** Header */
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struct ena_acq_header header;
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/** Create submission queue */
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struct ena_create_sq_rsp create_sq;
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/** Destroy submission queue */
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struct ena_destroy_sq_rsp destroy_sq;
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/** Create completion queue */
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struct ena_create_cq_rsp create_cq;
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/** Destroy completion queue */
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struct ena_destroy_cq_rsp destroy_cq;
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/** Get feature */
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struct ena_get_feature_rsp get_feature;
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/** Get statistics */
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struct ena_get_stats_rsp get_stats;
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/** Padding */
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uint8_t pad[64];
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};
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/** Admin queue */
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struct ena_aq {
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/** Requests */
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union ena_aq_req *req;
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/** Producer counter */
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unsigned int prod;
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};
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/** Admin completion queue */
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struct ena_acq {
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/** Responses */
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union ena_acq_rsp *rsp;
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/** Consumer counter */
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unsigned int cons;
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/** Phase */
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unsigned int phase;
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};
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/** Transmit submission queue entry */
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struct ena_tx_sqe {
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/** Length */
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uint16_t len;
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/** Reserved */
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uint8_t reserved_a;
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/** Flags */
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uint8_t flags;
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/** Reserved */
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uint8_t reserved_b[3];
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/** Request identifier */
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uint8_t id;
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/** Address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Receive submission queue entry */
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struct ena_rx_sqe {
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/** Length */
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uint16_t len;
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/** Reserved */
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uint8_t reserved_a;
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/** Flags */
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uint8_t flags;
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/** Request identifier */
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uint16_t id;
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/** Reserved */
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uint8_t reserved_b[2];
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/** Address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Submission queue ownership phase flag */
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#define ENA_SQE_PHASE 0x01
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/** This is the first descriptor */
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#define ENA_SQE_FIRST 0x04
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/** This is the last descriptor */
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#define ENA_SQE_LAST 0x08
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/** Request completion */
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#define ENA_SQE_CPL 0x10
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/** Transmit completion queue entry */
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struct ena_tx_cqe {
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/** Request identifier */
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uint16_t id;
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/** Status */
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uint8_t status;
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/** Flags */
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uint8_t flags;
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/** Reserved */
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uint8_t reserved[2];
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/** Consumer index */
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uint16_t cons;
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} __attribute__ (( packed ));
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/** Receive completion queue entry */
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struct ena_rx_cqe {
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/** Reserved */
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uint8_t reserved_a[3];
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/** Flags */
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uint8_t flags;
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/** Length */
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uint16_t len;
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/** Request identifier */
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uint16_t id;
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/** Reserved */
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uint8_t reserved_b[8];
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} __attribute__ (( packed ));
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/** Completion queue ownership phase flag */
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#define ENA_CQE_PHASE 0x01
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/** Submission queue */
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struct ena_sq {
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/** Entries */
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union {
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/** Transmit submission queue entries */
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struct ena_tx_sqe *tx;
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/** Receive submission queue entries */
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struct ena_rx_sqe *rx;
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/** Raw data */
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void *raw;
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} sqe;
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/** Doorbell register offset */
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unsigned int doorbell;
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/** Total length of entries */
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size_t len;
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/** Producer counter */
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unsigned int prod;
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/** Phase */
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unsigned int phase;
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/** Submission queue identifier */
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uint16_t id;
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/** Direction */
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uint8_t direction;
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/** Number of entries */
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uint8_t count;
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};
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/**
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* Initialise submission queue
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*
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* @v sq Submission queue
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* @v direction Direction
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* @v count Number of entries
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* @v size Size of each entry
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*/
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static inline __attribute__ (( always_inline )) void
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ena_sq_init ( struct ena_sq *sq, unsigned int direction, unsigned int count,
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size_t size ) {
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sq->len = ( count * size );
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sq->direction = direction;
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sq->count = count;
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}
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/** Completion queue */
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struct ena_cq {
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/** Entries */
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union {
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/** Transmit completion queue entries */
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struct ena_tx_cqe *tx;
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/** Receive completion queue entries */
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struct ena_rx_cqe *rx;
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/** Raw data */
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void *raw;
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} cqe;
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/** Doorbell register offset */
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unsigned int doorbell;
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/** Total length of entries */
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size_t len;
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/** Consumer counter */
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unsigned int cons;
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/** Phase */
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unsigned int phase;
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/** Completion queue identifier */
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uint16_t id;
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/** Entry size (in 32-bit words) */
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uint8_t size;
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/** Requested number of entries */
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uint8_t requested;
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/** Actual number of entries */
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uint8_t actual;
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/** Actual number of entries minus one */
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uint8_t mask;
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};
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/**
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* Initialise completion queue
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*
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* @v cq Completion queue
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* @v count Number of entries
|
||||
* @v size Size of each entry
|
||||
*/
|
||||
static inline __attribute__ (( always_inline )) void
|
||||
ena_cq_init ( struct ena_cq *cq, unsigned int count, size_t size ) {
|
||||
|
||||
cq->len = ( count * size );
|
||||
cq->size = ( size / sizeof ( uint32_t ) );
|
||||
cq->requested = count;
|
||||
}
|
||||
|
||||
/** Queue pair */
|
||||
struct ena_qp {
|
||||
/** Submission queue */
|
||||
struct ena_sq sq;
|
||||
/** Completion queue */
|
||||
struct ena_cq cq;
|
||||
};
|
||||
|
||||
/** An ENA network card */
|
||||
struct ena_nic {
|
||||
/** Registers */
|
||||
void *regs;
|
||||
/** Admin queue */
|
||||
struct ena_aq aq;
|
||||
/** Admin completion queue */
|
||||
struct ena_acq acq;
|
||||
/** Transmit queue */
|
||||
struct ena_qp tx;
|
||||
/** Receive queue */
|
||||
struct ena_qp rx;
|
||||
/** Receive I/O buffers */
|
||||
struct io_buffer *rx_iobuf[ENA_RX_COUNT];
|
||||
};
|
||||
|
||||
#endif /* _ENA_H */
|
||||
|
|
@ -202,6 +202,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
|
|||
#define ERRFILE_exanic ( ERRFILE_DRIVER | 0x00c60000 )
|
||||
#define ERRFILE_smscusb ( ERRFILE_DRIVER | 0x00c70000 )
|
||||
#define ERRFILE_lan78xx ( ERRFILE_DRIVER | 0x00c80000 )
|
||||
#define ERRFILE_ena ( ERRFILE_DRIVER | 0x00c90000 )
|
||||
|
||||
#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
|
||||
#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )
|
||||
|
|
|
|||
Loading…
Reference in New Issue