mirror of https://github.com/ipxe/ipxe.git
[realtek] Replace driver for Realtek Gigabit NICs
Tested-by: Thomas Miletich <thomas.miletich@gmail.com> Debugged-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Robin Smidsrød <robin@smidsrod.no> Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/6/head
Michael Brown
parent
9b2aabe534
commit
2a0154db5b
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/*
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* Copyright (c) 2008 Marty Connor <mdc@etherboot.org>
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* Copyright (c) 2008 Entity Cyber, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* This driver is based on rtl8169 data sheets and work by:
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*
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* Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
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* Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
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* Copyright (c) a lot of people too. Please respect their work.
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#ifndef _R8169_H_
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#define _R8169_H_
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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/** FIXME: include/linux/pci_regs.h has these PCI regs, maybe
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we need such a file in iPXE?
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**/
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#define PCI_EXP_DEVCTL 8 /* Device Control */
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#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
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#define PCI_EXP_LNKCTL 16 /* Link Control */
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#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
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#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
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/** FIXME: update mii.h in src/include/mii.h from Linux sources
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so we don't have to include these definitiions.
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**/
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/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
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#define SPEED_10 10
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#define SPEED_100 100
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#define SPEED_1000 1000
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#define SPEED_2500 2500
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#define SPEED_10000 10000
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/* Duplex, half or full. */
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#define DUPLEX_HALF 0x00
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#define DUPLEX_FULL 0x01
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#define AUTONEG_DISABLE 0x00
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#define AUTONEG_ENABLE 0x01
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/* MAC address length */
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#define MAC_ADDR_LEN 6
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#define MAX_READ_REQUEST_SHIFT 12
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#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
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#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
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#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
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#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
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#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
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#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
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#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
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#define R8169_REGS_SIZE 256
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#define R8169_NAPI_WEIGHT 64
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#define NUM_TX_DESC 8 /* Number of Tx descriptor registers */
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#define NUM_RX_DESC 8 /* Number of Rx descriptor registers */
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#define RX_BUF_SIZE 1536 /* Rx Buffer size */
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#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
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#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
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#define TX_RING_ALIGN 256
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#define RX_RING_ALIGN 256
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#define RTL8169_TX_TIMEOUT (6*HZ)
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#define RTL8169_PHY_TIMEOUT (10*HZ)
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#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
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#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
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#define RTL_EEPROM_SIG_ADDR 0x0000
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/* write/read MMIO register */
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#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
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#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
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#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
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#define RTL_R8(reg) readb (ioaddr + (reg))
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#define RTL_R16(reg) readw (ioaddr + (reg))
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#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
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enum mac_version {
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RTL_GIGA_MAC_VER_01 = 0x01, // 8169
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RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
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RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
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RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
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RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
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RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
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RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
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RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
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RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
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RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
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RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
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RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
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RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
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RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
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RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
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RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
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RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
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RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
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RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
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RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
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RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
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RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
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RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
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RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
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RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
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};
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#define _R(NAME,MAC,MASK) \
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{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
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static const struct {
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const char *name;
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u8 mac_version;
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u32 RxConfigMask; /* Clears the bits supported by this chip */
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} rtl_chip_info[] = {
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_R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
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_R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
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_R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
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_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
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_R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
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_R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
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_R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
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_R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
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_R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
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_R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
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};
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#undef _R
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enum cfg_version {
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RTL_CFG_0 = 0x00,
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RTL_CFG_1,
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RTL_CFG_2
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};
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#if 0
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/** Device Table from Linux Driver **/
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static struct pci_device_id rtl8169_pci_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
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{ PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
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{ PCI_VENDOR_ID_LINKSYS, 0x1032,
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PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
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{ 0x0001, 0x8168,
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PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
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{0,},
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};
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#endif
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enum rtl_registers {
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MAC0 = 0, /* Ethernet hardware address. */
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MAC4 = 4,
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MAR0 = 8, /* Multicast filter. */
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CounterAddrLow = 0x10,
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CounterAddrHigh = 0x14,
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TxDescStartAddrLow = 0x20,
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TxDescStartAddrHigh = 0x24,
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TxHDescStartAddrLow = 0x28,
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TxHDescStartAddrHigh = 0x2c,
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FLASH = 0x30,
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ERSR = 0x36,
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ChipCmd = 0x37,
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TxPoll = 0x38,
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IntrMask = 0x3c,
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IntrStatus = 0x3e,
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TxConfig = 0x40,
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RxConfig = 0x44,
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RxMissed = 0x4c,
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Cfg9346 = 0x50,
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Config0 = 0x51,
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Config1 = 0x52,
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Config2 = 0x53,
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Config3 = 0x54,
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Config4 = 0x55,
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Config5 = 0x56,
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MultiIntr = 0x5c,
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PHYAR = 0x60,
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PHYstatus = 0x6c,
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RxMaxSize = 0xda,
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CPlusCmd = 0xe0,
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IntrMitigate = 0xe2,
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RxDescAddrLow = 0xe4,
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RxDescAddrHigh = 0xe8,
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EarlyTxThres = 0xec,
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FuncEvent = 0xf0,
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FuncEventMask = 0xf4,
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FuncPresetState = 0xf8,
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FuncForceEvent = 0xfc,
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};
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enum rtl8110_registers {
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TBICSR = 0x64,
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TBI_ANAR = 0x68,
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TBI_LPAR = 0x6a,
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};
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enum rtl8168_8101_registers {
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CSIDR = 0x64,
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CSIAR = 0x68,
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#define CSIAR_FLAG 0x80000000
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#define CSIAR_WRITE_CMD 0x80000000
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#define CSIAR_BYTE_ENABLE 0x0f
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#define CSIAR_BYTE_ENABLE_SHIFT 12
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#define CSIAR_ADDR_MASK 0x0fff
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EPHYAR = 0x80,
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#define EPHYAR_FLAG 0x80000000
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#define EPHYAR_WRITE_CMD 0x80000000
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#define EPHYAR_REG_MASK 0x1f
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#define EPHYAR_REG_SHIFT 16
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#define EPHYAR_DATA_MASK 0xffff
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DBG_REG = 0xd1,
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#define FIX_NAK_1 (1 << 4)
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#define FIX_NAK_2 (1 << 3)
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};
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enum rtl_register_content {
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/* InterruptStatusBits */
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SYSErr = 0x8000,
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PCSTimeout = 0x4000,
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SWInt = 0x0100,
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TxDescUnavail = 0x0080,
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RxFIFOOver = 0x0040,
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LinkChg = 0x0020,
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RxOverflow = 0x0010,
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TxErr = 0x0008,
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TxOK = 0x0004,
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RxErr = 0x0002,
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RxOK = 0x0001,
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/* RxStatusDesc */
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RxFOVF = (1 << 23),
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RxRWT = (1 << 22),
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RxRES = (1 << 21),
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RxRUNT = (1 << 20),
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RxCRC = (1 << 19),
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/* ChipCmdBits */
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CmdReset = 0x10,
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CmdRxEnb = 0x08,
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CmdTxEnb = 0x04,
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RxBufEmpty = 0x01,
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/* TXPoll register p.5 */
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HPQ = 0x80, /* Poll cmd on the high prio queue */
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NPQ = 0x40, /* Poll cmd on the low prio queue */
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FSWInt = 0x01, /* Forced software interrupt */
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/* Cfg9346Bits */
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Cfg9346_Lock = 0x00,
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Cfg9346_Unlock = 0xc0,
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/* rx_mode_bits */
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0x08,
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AcceptMulticast = 0x04,
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AcceptMyPhys = 0x02,
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AcceptAllPhys = 0x01,
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/* RxConfigBits */
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RxCfgFIFOShift = 13,
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RxCfgDMAShift = 8,
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/* TxConfigBits */
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TxInterFrameGapShift = 24,
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TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
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/* Config1 register p.24 */
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LEDS1 = (1 << 7),
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LEDS0 = (1 << 6),
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MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
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Speed_down = (1 << 4),
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MEMMAP = (1 << 3),
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IOMAP = (1 << 2),
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VPD = (1 << 1),
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PMEnable = (1 << 0), /* Power Management Enable */
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/* Config2 register p. 25 */
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PCI_Clock_66MHz = 0x01,
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PCI_Clock_33MHz = 0x00,
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/* Config3 register p.25 */
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MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
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LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
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Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
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/* Config5 register p.27 */
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BWF = (1 << 6), /* Accept Broadcast wakeup frame */
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MWF = (1 << 5), /* Accept Multicast wakeup frame */
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UWF = (1 << 4), /* Accept Unicast wakeup frame */
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LanWake = (1 << 1), /* LanWake enable/disable */
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PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
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/* TBICSR p.28 */
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TBIReset = 0x80000000,
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TBILoopback = 0x40000000,
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TBINwEnable = 0x20000000,
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TBINwRestart = 0x10000000,
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TBILinkOk = 0x02000000,
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TBINwComplete = 0x01000000,
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/* CPlusCmd p.31 */
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EnableBist = (1 << 15), // 8168 8101
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Mac_dbgo_oe = (1 << 14), // 8168 8101
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Normal_mode = (1 << 13), // unused
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Force_half_dup = (1 << 12), // 8168 8101
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Force_rxflow_en = (1 << 11), // 8168 8101
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Force_txflow_en = (1 << 10), // 8168 8101
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Cxpl_dbg_sel = (1 << 9), // 8168 8101
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ASF = (1 << 8), // 8168 8101
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PktCntrDisable = (1 << 7), // 8168 8101
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Mac_dbgo_sel = 0x001c, // 8168
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RxVlan = (1 << 6),
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RxChkSum = (1 << 5),
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PCIDAC = (1 << 4),
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PCIMulRW = (1 << 3),
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INTT_0 = 0x0000, // 8168
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INTT_1 = 0x0001, // 8168
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INTT_2 = 0x0002, // 8168
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INTT_3 = 0x0003, // 8168
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/* rtl8169_PHYstatus */
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TBI_Enable = 0x80,
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TxFlowCtrl = 0x40,
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RxFlowCtrl = 0x20,
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_1000bpsF = 0x10,
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_100bps = 0x08,
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_10bps = 0x04,
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LinkStatus = 0x02,
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FullDup = 0x01,
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/* _TBICSRBit */
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TBILinkOK = 0x02000000,
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/* DumpCounterCommand */
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CounterDump = 0x8,
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};
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enum desc_status_bit {
|
||||
DescOwn = (1 << 31), /* Descriptor is owned by NIC */
|
||||
RingEnd = (1 << 30), /* End of descriptor ring */
|
||||
FirstFrag = (1 << 29), /* First segment of a packet */
|
||||
LastFrag = (1 << 28), /* Final segment of a packet */
|
||||
|
||||
/* Tx private */
|
||||
LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
|
||||
MSSShift = 16, /* MSS value position */
|
||||
MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
|
||||
IPCS = (1 << 18), /* Calculate IP checksum */
|
||||
UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
|
||||
TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
|
||||
TxVlanTag = (1 << 17), /* Add VLAN tag */
|
||||
|
||||
/* Rx private */
|
||||
PID1 = (1 << 18), /* Protocol ID bit 1/2 */
|
||||
PID0 = (1 << 17), /* Protocol ID bit 2/2 */
|
||||
|
||||
#define RxProtoUDP (PID1)
|
||||
#define RxProtoTCP (PID0)
|
||||
#define RxProtoIP (PID1 | PID0)
|
||||
#define RxProtoMask RxProtoIP
|
||||
|
||||
IPFail = (1 << 16), /* IP checksum failed */
|
||||
UDPFail = (1 << 15), /* UDP/IP checksum failed */
|
||||
TCPFail = (1 << 14), /* TCP/IP checksum failed */
|
||||
RxVlanTag = (1 << 16), /* VLAN tag available */
|
||||
};
|
||||
|
||||
#define RsvdMask 0x3fffc000
|
||||
|
||||
struct TxDesc {
|
||||
volatile uint32_t opts1;
|
||||
volatile uint32_t opts2;
|
||||
volatile uint32_t addr_lo;
|
||||
volatile uint32_t addr_hi;
|
||||
};
|
||||
|
||||
struct RxDesc {
|
||||
volatile uint32_t opts1;
|
||||
volatile uint32_t opts2;
|
||||
volatile uint32_t addr_lo;
|
||||
volatile uint32_t addr_hi;
|
||||
};
|
||||
|
||||
enum features {
|
||||
RTL_FEATURE_WOL = (1 << 0),
|
||||
RTL_FEATURE_MSI = (1 << 1),
|
||||
RTL_FEATURE_GMII = (1 << 2),
|
||||
};
|
||||
|
||||
static void rtl_hw_start_8169(struct net_device *);
|
||||
static void rtl_hw_start_8168(struct net_device *);
|
||||
static void rtl_hw_start_8101(struct net_device *);
|
||||
|
||||
struct rtl8169_private {
|
||||
|
||||
struct pci_device *pci_dev;
|
||||
struct net_device *netdev;
|
||||
uint8_t *hw_addr;
|
||||
void *mmio_addr;
|
||||
uint32_t irqno;
|
||||
|
||||
int chipset;
|
||||
int mac_version;
|
||||
u16 intr_event;
|
||||
|
||||
struct io_buffer *tx_iobuf[NUM_TX_DESC];
|
||||
struct io_buffer *rx_iobuf[NUM_RX_DESC];
|
||||
|
||||
struct TxDesc *tx_base;
|
||||
struct RxDesc *rx_base;
|
||||
|
||||
uint32_t tx_curr;
|
||||
uint32_t rx_curr;
|
||||
|
||||
uint32_t tx_tail;
|
||||
|
||||
uint32_t tx_fill_ctr;
|
||||
|
||||
u16 cp_cmd;
|
||||
|
||||
int phy_auto_nego_reg;
|
||||
int phy_1000_ctrl_reg;
|
||||
|
||||
int ( *set_speed ) (struct net_device *, u8 autoneg, u16 speed, u8 duplex );
|
||||
void ( *phy_reset_enable ) ( void *ioaddr );
|
||||
void ( *hw_start ) ( struct net_device * );
|
||||
unsigned int ( *phy_reset_pending ) ( void *ioaddr );
|
||||
unsigned int ( *link_ok ) ( void *ioaddr );
|
||||
|
||||
int pcie_cap;
|
||||
|
||||
unsigned features;
|
||||
|
||||
};
|
||||
|
||||
static const unsigned int rtl8169_rx_config =
|
||||
(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
|
||||
|
||||
#endif /* _R8169_H_ */
|
||||
|
||||
/*
|
||||
* Local variables:
|
||||
* c-basic-offset: 8
|
||||
* c-indent-level: 8
|
||||
* tab-width: 8
|
||||
* End:
|
||||
*/
|
||||
|
|
@ -0,0 +1,779 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
|
||||
*
|
||||
* (EEPROM code originally implemented for rtl8139.c)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
* 02110-1301, USA.
|
||||
*/
|
||||
|
||||
FILE_LICENCE ( GPL2_OR_LATER );
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include <errno.h>
|
||||
#include <byteswap.h>
|
||||
#include <ipxe/netdevice.h>
|
||||
#include <ipxe/ethernet.h>
|
||||
#include <ipxe/if_ether.h>
|
||||
#include <ipxe/iobuf.h>
|
||||
#include <ipxe/malloc.h>
|
||||
#include <ipxe/pci.h>
|
||||
#include <ipxe/nvs.h>
|
||||
#include <ipxe/threewire.h>
|
||||
#include <ipxe/bitbash.h>
|
||||
#include <ipxe/mii.h>
|
||||
#include "realtek.h"
|
||||
|
||||
/** @file
|
||||
*
|
||||
* Realtek 10/100/1000 network card driver
|
||||
*
|
||||
* Based on the following datasheets:
|
||||
*
|
||||
* http://www.datasheetarchive.com/dl/Datasheets-8/DSA-153536.pdf
|
||||
* http://www.datasheetarchive.com/indexdl/Datasheet-028/DSA00494723.pdf
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* EEPROM interface
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** Pin mapping for SPI bit-bashing interface */
|
||||
static const uint8_t realtek_eeprom_bits[] = {
|
||||
[SPI_BIT_SCLK] = RTL_9346CR_EESK,
|
||||
[SPI_BIT_MOSI] = RTL_9346CR_EEDI,
|
||||
[SPI_BIT_MISO] = RTL_9346CR_EEDO,
|
||||
[SPI_BIT_SS(0)] = ( RTL_9346CR_EECS | RTL_9346CR_EEM1 ),
|
||||
};
|
||||
|
||||
/**
|
||||
* Read input bit
|
||||
*
|
||||
* @v basher Bit-bashing interface
|
||||
* @v bit_id Bit number
|
||||
* @ret zero Input is a logic 0
|
||||
* @ret non-zero Input is a logic 1
|
||||
*/
|
||||
static int realtek_spi_read_bit ( struct bit_basher *basher,
|
||||
unsigned int bit_id ) {
|
||||
struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
|
||||
spibit.basher );
|
||||
uint8_t mask = realtek_eeprom_bits[bit_id];
|
||||
uint8_t reg;
|
||||
|
||||
reg = readb ( rtl->regs + RTL_9346CR );
|
||||
return ( reg & mask );
|
||||
}
|
||||
|
||||
/**
|
||||
* Set/clear output bit
|
||||
*
|
||||
* @v basher Bit-bashing interface
|
||||
* @v bit_id Bit number
|
||||
* @v data Value to write
|
||||
*/
|
||||
static void realtek_spi_write_bit ( struct bit_basher *basher,
|
||||
unsigned int bit_id, unsigned long data ) {
|
||||
struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
|
||||
spibit.basher );
|
||||
uint8_t mask = realtek_eeprom_bits[bit_id];
|
||||
uint8_t reg;
|
||||
|
||||
reg = readb ( rtl->regs + RTL_9346CR );
|
||||
reg &= ~mask;
|
||||
reg |= ( data & mask );
|
||||
writeb ( reg, rtl->regs + RTL_9346CR );
|
||||
}
|
||||
|
||||
/** SPI bit-bashing interface */
|
||||
static struct bit_basher_operations realtek_basher_ops = {
|
||||
.read = realtek_spi_read_bit,
|
||||
.write = realtek_spi_write_bit,
|
||||
};
|
||||
|
||||
/**
|
||||
* Initialise EEPROM
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void realtek_init_eeprom ( struct net_device *netdev ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
|
||||
/* Initialise SPI bit-bashing interface */
|
||||
rtl->spibit.basher.op = &realtek_basher_ops;
|
||||
rtl->spibit.bus.mode = SPI_MODE_THREEWIRE;
|
||||
init_spi_bit_basher ( &rtl->spibit );
|
||||
|
||||
/* Detect EEPROM type and initialise three-wire device */
|
||||
if ( readl ( rtl->regs + RTL_RCR ) & RTL_RCR_9356SEL ) {
|
||||
DBGC ( rtl, "REALTEK %p EEPROM is a 93C56\n", rtl );
|
||||
init_at93c56 ( &rtl->eeprom, 16 );
|
||||
} else {
|
||||
DBGC ( rtl, "REALTEK %p EEPROM is a 93C46\n", rtl );
|
||||
init_at93c46 ( &rtl->eeprom, 16 );
|
||||
}
|
||||
rtl->eeprom.bus = &rtl->spibit.bus;
|
||||
|
||||
/* Initialise space for non-volatile options, if available
|
||||
*
|
||||
* We use offset 0x40 (i.e. address 0x20), length 0x40. This
|
||||
* block is marked as VPD in the Realtek datasheets, so we use
|
||||
* it only if we detect that the card is not supporting VPD.
|
||||
*/
|
||||
if ( readb ( rtl->regs + RTL_CONFIG1 ) & RTL_CONFIG1_VPD ) {
|
||||
DBGC ( rtl, "REALTEK %p EEPROM in use for VPD; cannot use "
|
||||
"for options\n", rtl );
|
||||
} else {
|
||||
nvo_init ( &rtl->nvo, &rtl->eeprom.nvs, RTL_EEPROM_VPD,
|
||||
RTL_EEPROM_VPD_LEN, NULL, &netdev->refcnt );
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* MII interface
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* Read from MII register
|
||||
*
|
||||
* @v mii MII interface
|
||||
* @v reg Register address
|
||||
* @ret value Data read, or negative error
|
||||
*/
|
||||
static int realtek_mii_read ( struct mii_interface *mii, unsigned int reg ) {
|
||||
struct realtek_nic *rtl = container_of ( mii, struct realtek_nic, mii );
|
||||
unsigned int i;
|
||||
uint32_t value;
|
||||
|
||||
/* Initiate read */
|
||||
writel ( RTL_PHYAR_VALUE ( 0, reg, 0 ), rtl->regs + RTL_PHYAR );
|
||||
|
||||
/* Wait for read to complete */
|
||||
for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
|
||||
|
||||
/* If read is not complete, delay 1us and retry */
|
||||
value = readl ( rtl->regs + RTL_PHYAR );
|
||||
if ( ! ( value & RTL_PHYAR_FLAG ) ) {
|
||||
udelay ( 1 );
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Return register value */
|
||||
return ( RTL_PHYAR_DATA ( value ) );
|
||||
}
|
||||
|
||||
DBGC ( rtl, "REALTEK %p timed out waiting for MII read\n", rtl );
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to MII register
|
||||
*
|
||||
* @v mii MII interface
|
||||
* @v reg Register address
|
||||
* @v data Data to write
|
||||
* @ret rc Return status code
|
||||
*/
|
||||
static int realtek_mii_write ( struct mii_interface *mii, unsigned int reg,
|
||||
unsigned int data) {
|
||||
struct realtek_nic *rtl = container_of ( mii, struct realtek_nic, mii );
|
||||
unsigned int i;
|
||||
|
||||
/* Initiate write */
|
||||
writel ( RTL_PHYAR_VALUE ( RTL_PHYAR_FLAG, reg, data ),
|
||||
rtl->regs + RTL_PHYAR );
|
||||
|
||||
/* Wait for write to complete */
|
||||
for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
|
||||
|
||||
/* If write is not complete, delay 1us and retry */
|
||||
if ( readl ( rtl->regs + RTL_PHYAR ) & RTL_PHYAR_FLAG ) {
|
||||
udelay ( 1 );
|
||||
continue;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
DBGC ( rtl, "REALTEK %p timed out waiting for MII write\n", rtl );
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/** Realtek MII operations */
|
||||
static struct mii_operations realtek_mii_operations = {
|
||||
.read = realtek_mii_read,
|
||||
.write = realtek_mii_write,
|
||||
};
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Device reset
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* Reset hardware
|
||||
*
|
||||
* @v rtl Realtek device
|
||||
* @ret rc Return status code
|
||||
*/
|
||||
static int realtek_reset ( struct realtek_nic *rtl ) {
|
||||
unsigned int i;
|
||||
|
||||
/* Issue reset */
|
||||
writeb ( RTL_CR_RST, rtl->regs + RTL_CR );
|
||||
|
||||
/* Wait for reset to complete */
|
||||
for ( i = 0 ; i < RTL_RESET_MAX_WAIT_MS ; i++ ) {
|
||||
|
||||
/* If reset is not complete, delay 1ms and retry */
|
||||
if ( readb ( rtl->regs + RTL_CR ) & RTL_CR_RST ) {
|
||||
mdelay ( 1 );
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Enable PCI Dual Address Cycle (for 64-bit systems) */
|
||||
writew ( ( RTL_CPCR_DAC | RTL_CPCR_MULRW ),
|
||||
rtl->regs + RTL_CPCR );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
DBGC ( rtl, "REALTEK %p timed out waiting for reset\n", rtl );
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Link state
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* Check link state
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void realtek_check_link ( struct net_device *netdev ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
|
||||
if ( readb ( rtl->regs + RTL_PHYSTATUS ) & RTL_PHYSTATUS_LINKSTS ) {
|
||||
netdev_link_up ( netdev );
|
||||
} else {
|
||||
netdev_link_down ( netdev );
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Network device interface
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* Create descriptor ring
|
||||
*
|
||||
* @v rtl Realtek device
|
||||
* @v ring Descriptor ring
|
||||
* @ret rc Return status code
|
||||
*/
|
||||
static int realtek_create_ring ( struct realtek_nic *rtl,
|
||||
struct realtek_ring *ring ) {
|
||||
physaddr_t address;
|
||||
|
||||
/* Allocate descriptor ring */
|
||||
ring->desc = malloc_dma ( ring->len, RTL_RING_ALIGN );
|
||||
if ( ! ring->desc )
|
||||
return -ENOMEM;
|
||||
|
||||
/* Initialise descriptor ring */
|
||||
memset ( ring->desc, 0, ring->len );
|
||||
|
||||
/* Program ring address */
|
||||
address = virt_to_bus ( ring->desc );
|
||||
writel ( ( address & 0xffffffffUL ), rtl->regs + ring->reg );
|
||||
if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
|
||||
writel ( ( ( ( uint64_t ) address ) >> 32 ),
|
||||
rtl->regs + ring->reg + 4 );
|
||||
}
|
||||
DBGC ( rtl, "REALTEK %p ring %02x is at [%08llx,%08llx)\n",
|
||||
rtl, ring->reg, ( ( unsigned long long ) address ),
|
||||
( ( unsigned long long ) address + ring->len ) );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Destroy descriptor ring
|
||||
*
|
||||
* @v rtl Realtek device
|
||||
* @v ring Descriptor ring
|
||||
*/
|
||||
static void realtek_destroy_ring ( struct realtek_nic *rtl,
|
||||
struct realtek_ring *ring ) {
|
||||
|
||||
/* Clear ring address */
|
||||
writel ( 0, rtl->regs + ring->reg );
|
||||
writel ( 0, rtl->regs + ring->reg + 4 );
|
||||
|
||||
/* Free descriptor ring */
|
||||
free_dma ( ring->desc, ring->len );
|
||||
ring->desc = NULL;
|
||||
ring->prod = 0;
|
||||
ring->cons = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Refill receive descriptor ring
|
||||
*
|
||||
* @v rtl Realtek device
|
||||
*/
|
||||
static void realtek_refill_rx ( struct realtek_nic *rtl ) {
|
||||
struct realtek_descriptor *rx;
|
||||
struct io_buffer *iobuf;
|
||||
unsigned int rx_idx;
|
||||
physaddr_t address;
|
||||
int is_last;
|
||||
|
||||
while ( ( rtl->rx.prod - rtl->rx.cons ) < RTL_NUM_RX_DESC ) {
|
||||
|
||||
/* Allocate I/O buffer */
|
||||
iobuf = alloc_iob ( RTL_RX_MAX_LEN );
|
||||
if ( ! iobuf ) {
|
||||
/* Wait for next refill */
|
||||
return;
|
||||
}
|
||||
|
||||
/* Get next receive descriptor */
|
||||
rx_idx = ( rtl->rx.prod++ % RTL_NUM_RX_DESC );
|
||||
is_last = ( rx_idx == ( RTL_NUM_RX_DESC - 1 ) );
|
||||
rx = &rtl->rx.desc[rx_idx];
|
||||
|
||||
/* Populate receive descriptor */
|
||||
address = virt_to_bus ( iobuf->data );
|
||||
rx->address = cpu_to_le64 ( address );
|
||||
rx->length = RTL_RX_MAX_LEN;
|
||||
wmb();
|
||||
rx->flags = ( cpu_to_le16 ( RTL_DESC_OWN ) |
|
||||
( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
|
||||
wmb();
|
||||
|
||||
/* Record I/O buffer */
|
||||
assert ( rtl->rx_iobuf[rx_idx] == NULL );
|
||||
rtl->rx_iobuf[rx_idx] = iobuf;
|
||||
|
||||
DBGC2 ( rtl, "REALTEK %p RX %d is [%llx,%llx)\n", rtl, rx_idx,
|
||||
( ( unsigned long long ) address ),
|
||||
( ( unsigned long long ) address + RTL_RX_MAX_LEN ) );
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Open network device
|
||||
*
|
||||
* @v netdev Network device
|
||||
* @ret rc Return status code
|
||||
*/
|
||||
static int realtek_open ( struct net_device *netdev ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
uint32_t rcr;
|
||||
int rc;
|
||||
|
||||
/* Create transmit descriptor ring */
|
||||
if ( ( rc = realtek_create_ring ( rtl, &rtl->tx ) ) != 0 )
|
||||
goto err_create_tx;
|
||||
|
||||
/* Create receive descriptor ring */
|
||||
if ( ( rc = realtek_create_ring ( rtl, &rtl->rx ) ) != 0 )
|
||||
goto err_create_rx;
|
||||
|
||||
/* Configure MTU */
|
||||
writew ( RTL_RX_MAX_LEN, rtl->regs + RTL_RMS );
|
||||
|
||||
/* Accept all packets */
|
||||
writel ( 0xffffffffUL, rtl->regs + RTL_MAR0 );
|
||||
writel ( 0xffffffffUL, rtl->regs + RTL_MAR4 );
|
||||
rcr = readl ( rtl->regs + RTL_RCR );
|
||||
writel ( ( rcr | RTL_RCR_AB | RTL_RCR_AM | RTL_RCR_APM | RTL_RCR_AAP ),
|
||||
rtl->regs + RTL_RCR );
|
||||
|
||||
/* Fill receive ring */
|
||||
realtek_refill_rx ( rtl );
|
||||
|
||||
/* Enable transmitter and receiver */
|
||||
writeb ( ( RTL_CR_TE | RTL_CR_RE ), rtl->regs + RTL_CR );
|
||||
|
||||
return 0;
|
||||
|
||||
realtek_destroy_ring ( rtl, &rtl->rx );
|
||||
err_create_rx:
|
||||
realtek_destroy_ring ( rtl, &rtl->tx );
|
||||
err_create_tx:
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* Close network device
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void realtek_close ( struct net_device *netdev ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
unsigned int i;
|
||||
|
||||
/* Disable receiver and transmitter */
|
||||
writeb ( 0, rtl->regs + RTL_CR );
|
||||
|
||||
/* Destroy receive descriptor ring */
|
||||
realtek_destroy_ring ( rtl, &rtl->rx );
|
||||
|
||||
/* Discard any unused receive buffers */
|
||||
for ( i = 0 ; i < RTL_NUM_RX_DESC ; i++ ) {
|
||||
if ( rtl->rx_iobuf[i] )
|
||||
free_iob ( rtl->rx_iobuf[i] );
|
||||
rtl->rx_iobuf[i] = NULL;
|
||||
}
|
||||
|
||||
/* Destroy transmit descriptor ring */
|
||||
realtek_destroy_ring ( rtl, &rtl->tx );
|
||||
}
|
||||
|
||||
/**
|
||||
* Transmit packet
|
||||
*
|
||||
* @v netdev Network device
|
||||
* @v iobuf I/O buffer
|
||||
* @ret rc Return status code
|
||||
*/
|
||||
static int realtek_transmit ( struct net_device *netdev,
|
||||
struct io_buffer *iobuf ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
struct realtek_descriptor *tx;
|
||||
unsigned int tx_idx;
|
||||
physaddr_t address;
|
||||
int is_last;
|
||||
|
||||
/* Get next transmit descriptor */
|
||||
if ( ( rtl->tx.prod - rtl->tx.cons ) >= RTL_NUM_TX_DESC ) {
|
||||
DBGC ( rtl, "REALTEK %p out of transmit descriptors\n", rtl );
|
||||
return -ENOBUFS;
|
||||
}
|
||||
tx_idx = ( rtl->tx.prod++ % RTL_NUM_TX_DESC );
|
||||
is_last = ( tx_idx == ( RTL_NUM_TX_DESC - 1 ) );
|
||||
tx = &rtl->tx.desc[tx_idx];
|
||||
|
||||
/* Populate transmit descriptor */
|
||||
address = virt_to_bus ( iobuf->data );
|
||||
tx->address = cpu_to_le64 ( address );
|
||||
tx->length = cpu_to_le16 ( iob_len ( iobuf ) );
|
||||
wmb();
|
||||
tx->flags = ( cpu_to_le16 ( RTL_DESC_OWN | RTL_DESC_FS | RTL_DESC_LS ) |
|
||||
( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
|
||||
wmb();
|
||||
|
||||
/* Notify card that there are packets ready to transmit */
|
||||
writeb ( RTL_TPPOLL_NPQ, rtl->regs + RTL_TPPOLL );
|
||||
|
||||
DBGC2 ( rtl, "REALTEK %p TX %d is [%llx,%llx)\n", rtl, tx_idx,
|
||||
( ( unsigned long long ) address ),
|
||||
( ( unsigned long long ) address + iob_len ( iobuf ) ) );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Poll for completed packets
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void realtek_poll_tx ( struct net_device *netdev ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
struct realtek_descriptor *tx;
|
||||
unsigned int tx_idx;
|
||||
|
||||
/* Check for completed packets */
|
||||
while ( rtl->tx.cons != rtl->tx.prod ) {
|
||||
|
||||
/* Get next transmit descriptor */
|
||||
tx_idx = ( rtl->tx.cons % RTL_NUM_TX_DESC );
|
||||
tx = &rtl->tx.desc[tx_idx];
|
||||
|
||||
/* Stop if descriptor is still in use */
|
||||
if ( tx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
|
||||
return;
|
||||
|
||||
DBGC2 ( rtl, "REALTEK %p TX %d complete\n", rtl, tx_idx );
|
||||
|
||||
/* Complete TX descriptor */
|
||||
netdev_tx_complete_next ( netdev );
|
||||
rtl->tx.cons++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Poll for received packets
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void realtek_poll_rx ( struct net_device *netdev ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
struct realtek_descriptor *rx;
|
||||
struct io_buffer *iobuf;
|
||||
unsigned int rx_idx;
|
||||
size_t len;
|
||||
|
||||
/* Check for received packets */
|
||||
while ( rtl->rx.cons != rtl->rx.prod ) {
|
||||
|
||||
/* Get next receive descriptor */
|
||||
rx_idx = ( rtl->rx.cons % RTL_NUM_RX_DESC );
|
||||
rx = &rtl->rx.desc[rx_idx];
|
||||
|
||||
/* Stop if descriptor is still in use */
|
||||
if ( rx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
|
||||
return;
|
||||
|
||||
/* Populate I/O buffer */
|
||||
iobuf = rtl->rx_iobuf[rx_idx];
|
||||
rtl->rx_iobuf[rx_idx] = NULL;
|
||||
len = ( le16_to_cpu ( rx->length ) & RTL_DESC_SIZE_MASK );
|
||||
iob_put ( iobuf, ( len - 4 /* strip CRC */ ) );
|
||||
|
||||
DBGC2 ( rtl, "REALTEK %p RX %d complete (length %zd)\n",
|
||||
rtl, rx_idx, len );
|
||||
|
||||
/* Hand off to network stack */
|
||||
if ( rx->flags & cpu_to_le16 ( RTL_DESC_RES ) ) {
|
||||
netdev_rx_err ( netdev, iobuf, -EIO );
|
||||
} else {
|
||||
netdev_rx ( netdev, iobuf );
|
||||
}
|
||||
rtl->rx.cons++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Poll for completed and received packets
|
||||
*
|
||||
* @v netdev Network device
|
||||
*/
|
||||
static void realtek_poll ( struct net_device *netdev ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
uint16_t isr;
|
||||
|
||||
/* Check for and acknowledge interrupts */
|
||||
isr = readw ( rtl->regs + RTL_ISR );
|
||||
if ( ! isr )
|
||||
return;
|
||||
writew ( isr, rtl->regs + RTL_ISR );
|
||||
|
||||
/* Poll for TX completions, if applicable */
|
||||
if ( isr & ( RTL_IRQ_TER | RTL_IRQ_TOK ) )
|
||||
realtek_poll_tx ( netdev );
|
||||
|
||||
/* Poll for RX completionsm, if applicable */
|
||||
if ( isr & ( RTL_IRQ_RER | RTL_IRQ_ROK ) )
|
||||
realtek_poll_rx ( netdev );
|
||||
|
||||
/* Check link state, if applicable */
|
||||
if ( isr & RTL_IRQ_PUN_LINKCHG )
|
||||
realtek_check_link ( netdev );
|
||||
|
||||
/* Refill RX ring */
|
||||
realtek_refill_rx ( rtl );
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable or disable interrupts
|
||||
*
|
||||
* @v netdev Network device
|
||||
* @v enable Interrupts should be enabled
|
||||
*/
|
||||
static void realtek_irq ( struct net_device *netdev, int enable ) {
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
uint16_t imr;
|
||||
|
||||
/* Set interrupt mask */
|
||||
imr = ( enable ? ( RTL_IRQ_PUN_LINKCHG | RTL_IRQ_TER | RTL_IRQ_TOK |
|
||||
RTL_IRQ_RER | RTL_IRQ_ROK ) : 0 );
|
||||
writew ( imr, rtl->regs + RTL_IMR );
|
||||
}
|
||||
|
||||
/** Realtek network device operations */
|
||||
static struct net_device_operations realtek_operations = {
|
||||
.open = realtek_open,
|
||||
.close = realtek_close,
|
||||
.transmit = realtek_transmit,
|
||||
.poll = realtek_poll,
|
||||
.irq = realtek_irq,
|
||||
};
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* PCI interface
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
* Probe PCI device
|
||||
*
|
||||
* @v pci PCI device
|
||||
* @ret rc Return status code
|
||||
*/
|
||||
static int realtek_probe ( struct pci_device *pci ) {
|
||||
struct net_device *netdev;
|
||||
struct realtek_nic *rtl;
|
||||
unsigned int i;
|
||||
int rc;
|
||||
|
||||
/* Allocate and initialise net device */
|
||||
netdev = alloc_etherdev ( sizeof ( *rtl ) );
|
||||
if ( ! netdev ) {
|
||||
rc = -ENOMEM;
|
||||
goto err_alloc;
|
||||
}
|
||||
netdev_init ( netdev, &realtek_operations );
|
||||
rtl = netdev->priv;
|
||||
pci_set_drvdata ( pci, netdev );
|
||||
netdev->dev = &pci->dev;
|
||||
memset ( rtl, 0, sizeof ( *rtl ) );
|
||||
realtek_init_ring ( &rtl->tx, RTL_NUM_TX_DESC, RTL_TNPDS );
|
||||
realtek_init_ring ( &rtl->rx, RTL_NUM_RX_DESC, RTL_RDSAR );
|
||||
|
||||
/* Fix up PCI device */
|
||||
adjust_pci_device ( pci );
|
||||
|
||||
/* Map registers */
|
||||
rtl->regs = ioremap ( pci->membase, RTL_BAR_SIZE );
|
||||
|
||||
/* Reset the NIC */
|
||||
if ( ( rc = realtek_reset ( rtl ) ) != 0 )
|
||||
goto err_reset;
|
||||
|
||||
/* Initialise EEPROM */
|
||||
realtek_init_eeprom ( netdev );
|
||||
|
||||
/* Read MAC address from EEPROM */
|
||||
if ( ( rc = nvs_read ( &rtl->eeprom.nvs, RTL_EEPROM_MAC,
|
||||
netdev->hw_addr, ETH_ALEN ) ) != 0 ) {
|
||||
DBGC ( rtl, "REALTEK %p could not read MAC address: %s\n",
|
||||
rtl, strerror ( rc ) );
|
||||
goto err_nvs_read;
|
||||
}
|
||||
|
||||
/* The EEPROM may not be present for onboard NICs. Fall back
|
||||
* to reading the current ID register value, which will
|
||||
* hopefully have been programmed by the platform firmware.
|
||||
*/
|
||||
if ( ! is_valid_ether_addr ( netdev->hw_addr ) ) {
|
||||
DBGC ( rtl, "REALTEK %p seems to have no EEPROM\n", rtl );
|
||||
for ( i = 0 ; i < ETH_ALEN ; i++ )
|
||||
netdev->hw_addr[i] = readb ( rtl->regs + RTL_IDR0 + i );
|
||||
}
|
||||
|
||||
/* Initialise and reset MII interface */
|
||||
mii_init ( &rtl->mii, &realtek_mii_operations );
|
||||
if ( ( rc = mii_reset ( &rtl->mii ) ) != 0 ) {
|
||||
DBGC ( rtl, "REALTEK %p could not reset MII: %s\n",
|
||||
rtl, strerror ( rc ) );
|
||||
goto err_mii_reset;
|
||||
}
|
||||
|
||||
/* Register network device */
|
||||
if ( ( rc = register_netdev ( netdev ) ) != 0 )
|
||||
goto err_register_netdev;
|
||||
|
||||
/* Set initial link state */
|
||||
realtek_check_link ( netdev );
|
||||
|
||||
/* Register non-volatile options, if applicable */
|
||||
if ( rtl->nvo.nvs ) {
|
||||
if ( ( rc = register_nvo ( &rtl->nvo,
|
||||
netdev_settings ( netdev ) ) ) != 0)
|
||||
goto err_register_nvo;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_register_nvo:
|
||||
unregister_netdev ( netdev );
|
||||
err_register_netdev:
|
||||
err_mii_reset:
|
||||
err_nvs_read:
|
||||
realtek_reset ( rtl );
|
||||
err_reset:
|
||||
netdev_nullify ( netdev );
|
||||
netdev_put ( netdev );
|
||||
err_alloc:
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* Remove PCI device
|
||||
*
|
||||
* @v pci PCI device
|
||||
*/
|
||||
static void realtek_remove ( struct pci_device *pci ) {
|
||||
struct net_device *netdev = pci_get_drvdata ( pci );
|
||||
struct realtek_nic *rtl = netdev->priv;
|
||||
|
||||
/* Unregister non-volatile options, if applicable */
|
||||
if ( rtl->nvo.nvs )
|
||||
unregister_nvo ( &rtl->nvo );
|
||||
|
||||
/* Unregister network device */
|
||||
unregister_netdev ( netdev );
|
||||
|
||||
/* Reset card */
|
||||
realtek_reset ( rtl );
|
||||
|
||||
/* Free network device */
|
||||
netdev_nullify ( netdev );
|
||||
netdev_put ( netdev );
|
||||
}
|
||||
|
||||
/** Realtek PCI device IDs */
|
||||
static struct pci_device_id realtek_nics[] = {
|
||||
PCI_ROM ( 0x10ec, 0x8129, "r8129", "RTL-8129", 0 ),
|
||||
PCI_ROM ( 0x10ec, 0x8136, "r8136", "RTL8101E/RTL8102E", 0 ),
|
||||
PCI_ROM ( 0x10ec, 0x8167, "r8167", "RTL-8110SC/8169SC", 0 ),
|
||||
PCI_ROM ( 0x10ec, 0x8168, "r8168", "RTL8111/8168B", 0 ),
|
||||
PCI_ROM ( 0x10ec, 0x8169, "r8169", "RTL-8169", 0 ),
|
||||
PCI_ROM ( 0x1186, 0x4300, "dge528t", "DGE-528T", 0 ),
|
||||
PCI_ROM ( 0x1259, 0xc107, "allied8169", "Allied Telesyn 8169", 0 ),
|
||||
PCI_ROM ( 0x16ec, 0x0116, "usr997902", "USR997902", 0 ),
|
||||
PCI_ROM ( 0x1737, 0x1032, "linksys8169","Linksys 8169", 0 ),
|
||||
PCI_ROM ( 0x0001, 0x8168, "clone8169", "Cloned 8169", 0 ),
|
||||
};
|
||||
|
||||
/** Realtek PCI driver */
|
||||
struct pci_driver realtek_driver __pci_driver = {
|
||||
.ids = realtek_nics,
|
||||
.id_count = ( sizeof ( realtek_nics ) / sizeof ( realtek_nics[0] ) ),
|
||||
.probe = realtek_probe,
|
||||
.remove = realtek_remove,
|
||||
};
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
#ifndef _REALTEK_H
|
||||
#define _REALTEK_H
|
||||
|
||||
/** @file
|
||||
*
|
||||
* Realtek 10/100/1000 network card driver
|
||||
*
|
||||
*/
|
||||
|
||||
FILE_LICENCE ( GPL2_OR_LATER );
|
||||
|
||||
#include <ipxe/spi.h>
|
||||
#include <ipxe/spi_bit.h>
|
||||
#include <ipxe/nvo.h>
|
||||
#include <ipxe/if_ether.h>
|
||||
|
||||
/** PCI memory BAR size */
|
||||
#define RTL_BAR_SIZE 0x100
|
||||
|
||||
/** A packet descriptor */
|
||||
struct realtek_descriptor {
|
||||
/** Buffer size */
|
||||
uint16_t length;
|
||||
/** Flags */
|
||||
uint16_t flags;
|
||||
/** Reserved */
|
||||
uint32_t reserved;
|
||||
/** Buffer address */
|
||||
uint64_t address;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** Descriptor buffer size mask */
|
||||
#define RTL_DESC_SIZE_MASK 0x3fff
|
||||
|
||||
/** Packet descriptor flags */
|
||||
enum realtek_descriptor_flags {
|
||||
/** Descriptor is owned by NIC */
|
||||
RTL_DESC_OWN = 0x8000,
|
||||
/** End of descriptor ring */
|
||||
RTL_DESC_EOR = 0x4000,
|
||||
/** First segment descriptor */
|
||||
RTL_DESC_FS = 0x2000,
|
||||
/** Last segment descriptor */
|
||||
RTL_DESC_LS = 0x1000,
|
||||
/** Receive error summary */
|
||||
RTL_DESC_RES = 0x0020,
|
||||
};
|
||||
|
||||
/** Descriptor ring alignment */
|
||||
#define RTL_RING_ALIGN 256
|
||||
|
||||
/** ID Register 0 (6 bytes) */
|
||||
#define RTL_IDR0 0x00
|
||||
|
||||
/** Multicast Register 0 (dword) */
|
||||
#define RTL_MAR0 0x08
|
||||
|
||||
/** Multicast Register 4 (dword) */
|
||||
#define RTL_MAR4 0x0c
|
||||
|
||||
/** Transmit Normal Priority Descriptors (qword) */
|
||||
#define RTL_TNPDS 0x20
|
||||
|
||||
/** Number of transmit descriptors */
|
||||
#define RTL_NUM_TX_DESC 4
|
||||
|
||||
/** Command Register (byte) */
|
||||
#define RTL_CR 0x37
|
||||
#define RTL_CR_RST 0x10 /**< Reset */
|
||||
#define RTL_CR_RE 0x08 /**< Receiver Enable */
|
||||
#define RTL_CR_TE 0x04 /**< Transmit Enable */
|
||||
|
||||
/** Maximum time to wait for a reset, in milliseconds */
|
||||
#define RTL_RESET_MAX_WAIT_MS 100
|
||||
|
||||
/** Transmit Priority Polling Register (byte) */
|
||||
#define RTL_TPPOLL 0x38
|
||||
#define RTL_TPPOLL_NPQ 0x40 /**< Normal Priority Queue Polling */
|
||||
|
||||
/** Interrupt Mask Register (word) */
|
||||
#define RTL_IMR 0x3c
|
||||
#define RTL_IRQ_PUN_LINKCHG 0x20 /**< Packet underrun / link change */
|
||||
#define RTL_IRQ_TER 0x08 /**< Transmit error */
|
||||
#define RTL_IRQ_TOK 0x04 /**< Transmit OK */
|
||||
#define RTL_IRQ_RER 0x02 /**< Receive error */
|
||||
#define RTL_IRQ_ROK 0x01 /**< Receive OK */
|
||||
|
||||
/** Interrupt Status Register (word) */
|
||||
#define RTL_ISR 0x3e
|
||||
|
||||
/** Receive (Rx) Configuration Register (dword) */
|
||||
#define RTL_RCR 0x44
|
||||
#define RTL_RCR_9356SEL 0x40 /**< EEPROM is a 93C56 */
|
||||
#define RTL_RCR_AB 0x08 /**< Accept broadcast packets */
|
||||
#define RTL_RCR_AM 0x04 /**< Accept multicast packets */
|
||||
#define RTL_RCR_APM 0x02 /**< Accept physical match packets */
|
||||
#define RTL_RCR_AAP 0x01 /**< Accept all packets */
|
||||
|
||||
/** 93C46 (93C56) Command Register (byte) */
|
||||
#define RTL_9346CR 0x50
|
||||
#define RTL_9346CR_EEM1 0x80 /**< Mode select bit 1 */
|
||||
#define RTL_9346CR_EEM0 0x40 /**< Mode select bit 0 */
|
||||
#define RTL_9346CR_EECS 0x08 /**< Chip select */
|
||||
#define RTL_9346CR_EESK 0x04 /**< Clock */
|
||||
#define RTL_9346CR_EEDI 0x02 /**< Data in */
|
||||
#define RTL_9346CR_EEDO 0x01 /**< Data out */
|
||||
|
||||
/** Word offset of MAC address within EEPROM */
|
||||
#define RTL_EEPROM_MAC ( 0x0e / 2 )
|
||||
|
||||
/** Word offset of VPD / non-volatile options within EEPROM */
|
||||
#define RTL_EEPROM_VPD ( 0x40 / 2 )
|
||||
|
||||
/** Length of VPD / non-volatile options within EEPROM */
|
||||
#define RTL_EEPROM_VPD_LEN 0x40
|
||||
|
||||
/** Configuration Register 1 (byte) */
|
||||
#define RTL_CONFIG1 0x52
|
||||
#define RTL_CONFIG1_VPD 0x02 /**< Vital Product Data enabled */
|
||||
|
||||
/** PHY Access Register (dword) */
|
||||
#define RTL_PHYAR 0x60
|
||||
#define RTL_PHYAR_FLAG 0x80000000UL /**< Read/write flag */
|
||||
|
||||
/** Construct PHY Access Register value */
|
||||
#define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) )
|
||||
|
||||
/** Extract PHY Access Register data */
|
||||
#define RTL_PHYAR_DATA( value ) ( (value) & 0xffff )
|
||||
|
||||
/** Maximum time to wait for PHY access, in microseconds */
|
||||
#define RTL_MII_MAX_WAIT_US 500
|
||||
|
||||
/** PHY (GMII, MII, or TBI) Status Register (byte) */
|
||||
#define RTL_PHYSTATUS 0x6c
|
||||
#define RTL_PHYSTATUS_LINKSTS 0x02 /**< Link ok */
|
||||
|
||||
/** RX Packet Maximum Size Register (word) */
|
||||
#define RTL_RMS 0xda
|
||||
|
||||
/** C+ Command Register (word) */
|
||||
#define RTL_CPCR 0xe0
|
||||
#define RTL_CPCR_DAC 0x10 /**< PCI Dual Address Cycle Enable */
|
||||
#define RTL_CPCR_MULRW 0x08 /**< PCI Multiple Read/Write Enable */
|
||||
|
||||
/** Receive Descriptor Start Address Register (qword) */
|
||||
#define RTL_RDSAR 0xe4
|
||||
|
||||
/** Number of receive descriptors */
|
||||
#define RTL_NUM_RX_DESC 4
|
||||
|
||||
/** Receive buffer length */
|
||||
#define RTL_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
|
||||
|
||||
/** A Realtek descriptor ring */
|
||||
struct realtek_ring {
|
||||
/** Descriptors */
|
||||
struct realtek_descriptor *desc;
|
||||
/** Producer index */
|
||||
unsigned int prod;
|
||||
/** Consumer index */
|
||||
unsigned int cons;
|
||||
|
||||
/** Descriptor start address register */
|
||||
unsigned int reg;
|
||||
/** Length (in bytes) */
|
||||
size_t len;
|
||||
};
|
||||
|
||||
/**
|
||||
* Initialise descriptor ring
|
||||
*
|
||||
* @v ring Descriptor ring
|
||||
* @v count Number of descriptors
|
||||
* @v reg Descriptor start address register
|
||||
*/
|
||||
static inline __attribute__ (( always_inline)) void
|
||||
realtek_init_ring ( struct realtek_ring *ring, unsigned int count,
|
||||
unsigned int reg ) {
|
||||
ring->len = ( count * sizeof ( ring->desc[0] ) );
|
||||
ring->reg = reg;
|
||||
}
|
||||
|
||||
/** A Realtek network card */
|
||||
struct realtek_nic {
|
||||
/** Registers */
|
||||
void *regs;
|
||||
/** SPI bit-bashing interface */
|
||||
struct spi_bit_basher spibit;
|
||||
/** EEPROM */
|
||||
struct spi_device eeprom;
|
||||
/** Non-volatile options */
|
||||
struct nvo_block nvo;
|
||||
/** MII interface */
|
||||
struct mii_interface mii;
|
||||
|
||||
/** Transmit descriptor ring */
|
||||
struct realtek_ring tx;
|
||||
/** Receive descriptor ring */
|
||||
struct realtek_ring rx;
|
||||
/** Receive I/O buffers */
|
||||
struct io_buffer *rx_iobuf[RTL_NUM_RX_DESC];
|
||||
};
|
||||
|
||||
#endif /* _REALTEK_H */
|
||||
|
|
@ -142,6 +142,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
|
|||
#define ERRFILE_ath ( ERRFILE_DRIVER | 0x00600000 )
|
||||
#define ERRFILE_vmxnet3 ( ERRFILE_DRIVER | 0x00610000 )
|
||||
#define ERRFILE_mii ( ERRFILE_DRIVER | 0x00620000 )
|
||||
#define ERRFILE_realtek ( ERRFILE_DRIVER | 0x00630000 )
|
||||
|
||||
#define ERRFILE_scsi ( ERRFILE_DRIVER | 0x00700000 )
|
||||
#define ERRFILE_arbel ( ERRFILE_DRIVER | 0x00710000 )
|
||||
|
|
|
|||
Loading…
Reference in New Issue