mirror of https://github.com/ipxe/ipxe.git
[bios] Provide a multiprocessor API for BIOS
Provide an implementation of the iPXE multiprocessor API for BIOS, based on sending broadcast INIT and SIPI interprocessor interrupts to start up all application processors. Signed-off-by: Michael Brown <mcb30@ipxe.org>pull/1174/head
Michael Brown
parent
a67f913d66
commit
1344e13a03
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@ -9,4 +9,6 @@
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/bios_mp.h>
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#endif /* _BITS_MP_H */
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@ -0,0 +1,32 @@
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#ifndef _IPXE_BIOS_MP_H
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#define _IPXE_BIOS_MP_H
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/** @file
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*
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* BIOS multiprocessor API implementation
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/io.h>
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#ifdef MPAPI_PCBIOS
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#define MPAPI_PREFIX_pcbios
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#else
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#define MPAPI_PREFIX_pcbios __pcbios_
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#endif
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/**
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* Calculate address as seen by a multiprocessor function
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*
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* @v address Address in boot processor address space
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* @ret address Address in application processor address space
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*/
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static inline __attribute__ (( always_inline )) mp_addr_t
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MPAPI_INLINE ( pcbios, mp_address ) ( void *address ) {
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return virt_to_phys ( address );
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}
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#endif /* _IPXE_BIOS_MP_H */
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@ -0,0 +1,172 @@
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/*
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* Copyright (C) 2024 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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* You can also choose to distribute this program under the terms of
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* the Unmodified Binary Distribution Licence (as given in the file
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* COPYING.UBDL), provided that you have satisfied its requirements.
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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/** @file
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*
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* BIOS multiprocessor API implementation
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*
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*/
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#include <registers.h>
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#include <ipxe/uaccess.h>
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#include <ipxe/timer.h>
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#include <ipxe/msr.h>
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#include <ipxe/mp.h>
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/** Local APIC base address MSR */
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#define MSR_APIC_BASE 0x0000001b
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/** Local APIC is in x2APIC mode */
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#define MSR_APIC_BASE_X2APIC 0x400
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/** Local APIC base address mask */
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#define MSR_APIC_BASE_MASK ( ~0xfffULL )
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/** Interrupt command register */
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#define APIC_ICR 0x0300
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/** Interrupt command register (x2APIC) */
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#define MSR_X2APIC_ICR 0x830
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/** Interrupt command register: send to all excluding self */
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#define APIC_ICR_ALL_NOT_SELF 0x000c0000
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/** Interrupt command register: level mode */
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#define APIC_ICR_LEVEL 0x00008000
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/** Interrupt command register: level asserted */
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#define APIC_ICR_LEVEL_ASSERT 0x00004000
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/** Interrupt command register: INIT */
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#define APIC_ICR_INIT 0x00000500
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/** Interrupt command register: SIPI */
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#define APIC_ICR_SIPI( vector ) ( 0x00000600 | (vector) )
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/** Time to wait for an IPI to complete */
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#define IPI_WAIT_MS 10
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/**
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* Startup IPI vector
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*
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* The real-mode startup IPI code must be copied to a page boundary in
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* base memory. We fairly arbitrarily choose to place this at 0x8000.
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*/
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#define SIPI_VECTOR 0x08
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/** Protected-mode startup IPI handler */
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extern void __asmcall mp_jump ( mp_addr_t func, mp_addr_t opaque );
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/**
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* Execute a multiprocessor function on the boot processor
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*
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* @v func Multiprocessor function
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* @v opaque Opaque data pointer
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*/
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static void bios_mp_exec_boot ( mp_func_t func, void *opaque ) {
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/* Call multiprocessor function with physical addressing */
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__asm__ __volatile__ ( PHYS_CODE ( "pushl %k2\n\t"
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"pushl %k1\n\t"
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"call *%k0\n\t"
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"addl $8, %%esp\n\t" )
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: : "r" ( mp_address ( mp_call ) ),
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"r" ( mp_address ( func ) ),
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"r" ( mp_address ( opaque ) ) );
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}
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/**
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* Send an interprocessor interrupt
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*
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* @v apic APIC base address
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* @v x2apic x2APIC mode enabled
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* @v icr Interrupt control register value
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*/
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static void bios_mp_ipi ( void *apic, int x2apic, uint32_t icr ) {
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/* Write ICR according to APIC/x2APIC mode */
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DBGC ( MSR_APIC_BASE, "BIOSMP sending IPI %#08x\n", icr );
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if ( x2apic ) {
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wrmsr ( MSR_X2APIC_ICR, icr );
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} else {
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writel ( icr, ( apic + APIC_ICR ) );
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}
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/* Allow plenty of time for delivery to complete */
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mdelay ( IPI_WAIT_MS );
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}
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/**
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* Start a multiprocessor function on all application processors
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*
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* @v func Multiprocessor function
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* @v opaque Opaque data pointer
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*/
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static void bios_mp_start_all ( mp_func_t func, void *opaque ) {
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struct i386_regs regs;
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uint64_t base;
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uint32_t ipi;
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void *apic;
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int x2apic;
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/* Prepare SIPI handler */
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regs.eax = mp_address ( func );
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regs.edx = mp_address ( opaque );
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setup_sipi ( SIPI_VECTOR, virt_to_phys ( mp_jump ), ®s );
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/* Get local APIC base address and mode */
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base = rdmsr ( MSR_APIC_BASE );
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x2apic = ( base & MSR_APIC_BASE_X2APIC );
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DBGC ( MSR_APIC_BASE, "BIOSMP local %sAPIC base %#llx\n",
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( x2apic ? "x2" : "" ), ( ( unsigned long long ) base ) );
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/* Map local APIC */
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apic = ioremap ( ( base & MSR_APIC_BASE_MASK ), PAGE_SIZE );
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if ( ! apic )
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goto err_ioremap;
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/* Assert INIT IPI */
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ipi = ( APIC_ICR_ALL_NOT_SELF | APIC_ICR_LEVEL |
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APIC_ICR_LEVEL_ASSERT | APIC_ICR_INIT );
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bios_mp_ipi ( apic, x2apic, ipi );
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/* Clear INIT IPI */
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ipi &= ~APIC_ICR_LEVEL_ASSERT;
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bios_mp_ipi ( apic, x2apic, ipi );
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/* Send SIPI */
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ipi = ( APIC_ICR_ALL_NOT_SELF | APIC_ICR_SIPI ( SIPI_VECTOR ) );
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bios_mp_ipi ( apic, x2apic, ipi );
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iounmap ( apic );
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err_ioremap:
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/* No way to handle errors: caller must check that
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* multiprocessor function executed as expected.
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*/
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}
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PROVIDE_MPAPI_INLINE ( pcbios, mp_address );
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PROVIDE_MPAPI ( pcbios, mp_exec_boot, bios_mp_exec_boot );
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PROVIDE_MPAPI ( pcbios, mp_start_all, bios_mp_start_all );
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@ -24,7 +24,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define TIME_RTC
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#define REBOOT_PCBIOS
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#define ACPI_RSDP
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#define MPAPI_NULL
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#define MPAPI_PCBIOS
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#ifdef __x86_64__
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#define IOMAP_PAGES
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