narenas
/
opengnsys_ipxe
mirror of https://github.com/ipxe/ipxe.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[rng] Check for TSC support before using RTC entropy source 

Signed-off-by: Michael Brown <mcb30@ipxe.org>
pull/373/head
Michael Brown 2021-05-12 10:24:00 +01:00
parent 13c1abe10a
commit 05fcf1a2f0
2 changed files with 14 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/x86/include/ipxe/cpuid.h
View File

@ -42,6 +42,9 @@ struct x86_features {
/** Hypervisor is present */
#define CPUID_FEATURES_INTEL_ECX_HYPERVISOR 0x80000000UL
/** TSC is present */
#define CPUID_FEATURES_INTEL_EDX_TSC 0x00000010UL
/** FXSAVE and FXRSTOR are supported */
#define CPUID_FEATURES_INTEL_EDX_FXSR 0x01000000UL

11
src/arch/x86/interface/pcbios/rtc_entropy.c
View File

@ -36,6 +36,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#include <biosint.h>
#include <pic8259.h>
#include <rtc.h>
#include <ipxe/cpuid.h>
#include <ipxe/entropy.h>
/** Maximum time to wait for an RTC interrupt, in milliseconds */
@ -174,8 +175,17 @@ static int rtc_entropy_check ( void ) {
* @ret rc Return status code
*/
static int rtc_entropy_enable ( void ) {
struct x86_features features;
int rc;
/* Check that TSC is supported */
x86_features ( &features );
if ( ! ( features.intel.edx & CPUID_FEATURES_INTEL_EDX_TSC ) ) {
DBGC ( &rtc_flag, "RTC has no TSC\n" );
rc = -ENOTSUP;
goto err_no_tsc;
}
/* Hook ISR and enable RTC interrupts */
rtc_hook_isr();
enable_irq ( RTC_IRQ );
@ -191,6 +201,7 @@ static int rtc_entropy_enable ( void ) {
rtc_disable_int();
disable_irq ( RTC_IRQ );
rtc_unhook_isr();
err_no_tsc:
return rc;
}